224 lines
7.0 KiB
LLVM
224 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32ZBKB
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; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64ZBKB
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; TODO: These tests can be optmised
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; fold (bitreverse(srl (bitreverse c), x)) -> (shl c, x)
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; fold (bitreverse(shl (bitreverse c), x)) -> (srl c, x)
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declare i8 @llvm.bitreverse.i8(i8)
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declare i16 @llvm.bitreverse.i16(i16)
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declare i32 @llvm.bitreverse.i32(i32)
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declare i64 @llvm.bitreverse.i64(i64)
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define i8 @test_bitreverse_srli_bitreverse_i8(i8 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i8:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 27
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 24
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i8:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 59
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 56
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; RV64ZBKB-NEXT: ret
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%1 = call i8 @llvm.bitreverse.i8(i8 %a)
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%2 = lshr i8 %1, 3
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%3 = call i8 @llvm.bitreverse.i8(i8 %2)
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ret i8 %3
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}
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define i16 @test_bitreverse_srli_bitreverse_i16(i16 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i16:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 23
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 16
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i16:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 55
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 48
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; RV64ZBKB-NEXT: ret
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%1 = call i16 @llvm.bitreverse.i16(i16 %a)
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%2 = lshr i16 %1, 7
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%3 = call i16 @llvm.bitreverse.i16(i16 %2)
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ret i16 %3
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}
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define i32 @test_bitreverse_srli_bitreverse_i32(i32 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i32:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 15
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 47
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 32
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; RV64ZBKB-NEXT: ret
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%1 = call i32 @llvm.bitreverse.i32(i32 %a)
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%2 = lshr i32 %1, 15
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%3 = call i32 @llvm.bitreverse.i32(i32 %2)
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ret i32 %3
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}
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define i64 @test_bitreverse_srli_bitreverse_i64(i64 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i64:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 1
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a1, a0
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; RV32ZBKB-NEXT: li a0, 0
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 33
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: ret
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%1 = call i64 @llvm.bitreverse.i64(i64 %a)
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%2 = lshr i64 %1, 33
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%3 = call i64 @llvm.bitreverse.i64(i64 %2)
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ret i64 %3
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}
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define i8 @test_bitreverse_shli_bitreverse_i8(i8 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i8:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 24
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; RV32ZBKB-NEXT: slli a0, a0, 3
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 24
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i8:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 56
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; RV64ZBKB-NEXT: slli a0, a0, 3
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 56
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; RV64ZBKB-NEXT: ret
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%1 = call i8 @llvm.bitreverse.i8(i8 %a)
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%2 = shl i8 %1, 3
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%3 = call i8 @llvm.bitreverse.i8(i8 %2)
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ret i8 %3
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}
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define i16 @test_bitreverse_shli_bitreverse_i16(i16 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i16:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 16
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; RV32ZBKB-NEXT: slli a0, a0, 7
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: srli a0, a0, 16
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i16:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 48
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; RV64ZBKB-NEXT: slli a0, a0, 7
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 48
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; RV64ZBKB-NEXT: ret
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%1 = call i16 @llvm.bitreverse.i16(i16 %a)
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%2 = shl i16 %1, 7
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%3 = call i16 @llvm.bitreverse.i16(i16 %2)
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ret i16 %3
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}
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define i32 @test_bitreverse_shli_bitreverse_i32(i32 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i32:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: slli a0, a0, 15
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 32
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; RV64ZBKB-NEXT: slli a0, a0, 15
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: srli a0, a0, 32
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; RV64ZBKB-NEXT: ret
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%1 = call i32 @llvm.bitreverse.i32(i32 %a)
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%2 = shl i32 %1, 15
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%3 = call i32 @llvm.bitreverse.i32(i32 %2)
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ret i32 %3
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}
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define i64 @test_bitreverse_shli_bitreverse_i64(i64 %a) nounwind {
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; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i64:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: rev8 a0, a1
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: slli a0, a0, 1
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; RV32ZBKB-NEXT: rev8 a0, a0
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; RV32ZBKB-NEXT: brev8 a0, a0
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; RV32ZBKB-NEXT: li a1, 0
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; RV32ZBKB-NEXT: ret
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;
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; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: slli a0, a0, 33
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; RV64ZBKB-NEXT: rev8 a0, a0
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; RV64ZBKB-NEXT: brev8 a0, a0
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; RV64ZBKB-NEXT: ret
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%1 = call i64 @llvm.bitreverse.i64(i64 %a)
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%2 = shl i64 %1, 33
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%3 = call i64 @llvm.bitreverse.i64(i64 %2)
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ret i64 %3
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}
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