OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/RISCV
History
Craig Topper aaad507546 [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 
When lowering GlobalAddressNodes, we were removing a non-zero offset and
creating a separate ADD.

It already comes out of SelectionDAGBuilder with a separate ADD. The
ADD was being removed by DAGCombiner.

This patch disables the DAG combine so we don't have to reverse it.
Test changes all look to be instruction order changes. Probably due
to different DAG node ordering.

Differential Revision: https://reviews.llvm.org/D126558
 		2022-05-27 11:05:18 -07:00
..
GlobalISel [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
intrinsics
…
rvv [RISCV] Allow compatible VTYPE in AVL Reg Forward cases 2022-05-26 08:50:35 -07:00
MachineSink-implicit-x0.mir Fix minor deficiency in machine-sink. 2021-11-12 08:01:13 +01:00
O0-pipeline.ll [RISCV] Add pre-emit pass to make more instructions compressible 2022-05-25 09:25:02 +01:00
O3-pipeline.ll Revert "[Propeller] Promote functions with propeller profiles to .text.hot." 2022-05-26 18:45:40 -07:00
add-before-shl.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
add-imm.ll [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns. 2021-08-18 11:07:11 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll [test][DAGCombine] Add more tests for carry diamond. NFC 2022-01-27 00:25:26 +01:00
addimm-mulimm.ll [RISCV] Remove tab character from test. Autogenerate CHECK lines. NFC 2022-02-25 11:37:27 -08:00
addrspacecast.ll
…
aext-to-sext.ll [RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64. 2022-04-11 14:38:39 -07:00
align-loops.ll [CodeGen] Add -align-loops 2021-08-04 12:45:18 -07:00
align.ll
…
alloca.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
alu8.ll [RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16), (XLen-16) + C) optimization. 2022-01-09 23:37:10 -08:00
alu16.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
alu32.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
alu64.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
analyze-branch.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
and.ll [RISCV] Select SRLI+SLLI for AND with leading ones mask 2022-03-16 02:10:57 +00:00
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
atomic-fence.ll
…
atomic-load-store.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
atomic-rmw.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
atomic-signext.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
attributes.ll [RISCV] Add combination crypto extensions in ISAInfo 2022-03-08 09:52:38 -08:00
bitreverse-shift.ll [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases 2022-03-30 11:46:42 -07:00
bittest.ll [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. 2022-05-11 11:13:17 -07:00
blockaddress.ll
…
branch-relaxation.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
branch.ll
…
bswap-bitreverse.ll [DAGCombiner] Fix bug in MatchBSwapHWordLow. 2022-05-18 09:23:18 -07:00
bswap-shift.ll [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases 2022-03-30 11:46:42 -07:00
byval.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
callee-saved-fpr64s.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
callee-saved-gprs.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-half.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-ilp32.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-ilp32d.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-lp64-lp64f-common.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-lp64.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-rv32f-ilp32.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
calls.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
compress-float.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
compress-inline-asm.ll
…
compress.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
copy-frameindex.mir [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
copysign-casts.ll [RISCV] Select SRLI+SLLI for AND with leading ones mask 2022-03-16 02:10:57 +00:00
ctlz-cttz-ctpop.ll [TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift. 2022-05-16 09:27:44 -07:00
disable-tail-calls.ll
…
disjoint.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
div-by-constant.ll [RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3). 2022-04-08 09:04:04 -07:00
div-pow2.ll [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT 2022-01-11 15:54:35 +08:00
div.ll [RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3). 2022-04-08 09:04:04 -07:00
double-arith-strict.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
double-arith.ll [RISCV] Select SRLI+SLLI for AND with leading ones mask 2022-03-16 02:10:57 +00:00
double-bitmanip-dagcombines.ll [RISCV] Select SRLI+SLLI for AND with leading ones mask 2022-03-16 02:10:57 +00:00
double-br-fcmp.ll [RISCV] Remove some TODOs in tests 2022-05-11 22:53:50 +08:00
double-calling-conv.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
double-convert-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
double-convert.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
double-fcmp-strict.ll [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range 2022-03-29 14:46:49 +08:00
double-fcmp.ll [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range 2022-03-29 14:46:49 +08:00
double-frem.ll [RISCV] Promote f16 frem with Zfh. 2021-11-10 17:35:07 -08:00
double-imm.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
double-intrinsics-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
double-intrinsics.ll [RISCV] Select SRLI+SLLI for AND with leading ones mask 2022-03-16 02:10:57 +00:00
double-isnan.ll
…
double-mem.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
double-previous-failure.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
double-round-conv-sat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
double-round-conv.ll [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn) 2022-01-11 09:05:57 -08:00
double-select-fcmp.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
double-stack-spill-restore.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
dwarf-eh.ll
…
elf-preemption.ll [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local 2021-05-11 11:29:45 -07:00
exception-pointer-register.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
fastcc-float.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
fastcc-int.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
fixed-vectors-vadd-vp-mask.ll [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations 2022-04-26 02:30:22 +00:00
fixed-vectors-vmul-vp-mask.ll [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations 2022-04-26 02:30:22 +00:00
fixed-vectors-vsub-vp-mask.ll [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations 2022-04-26 02:30:22 +00:00
fixups-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
float-arith-strict.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
float-arith.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
float-bit-preserving-dagcombines.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
float-bitmanip-dagcombines.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
float-br-fcmp.ll [RISCV] Remove some TODOs in tests 2022-05-11 22:53:50 +08:00
float-convert-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
float-convert.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
float-fcmp-strict.ll [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range 2022-03-29 14:46:49 +08:00
float-fcmp.ll [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range 2022-03-29 14:46:49 +08:00
float-frem.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-imm.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
float-intrinsics-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
float-intrinsics.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
float-isnan.ll
…
float-mem.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
float-round-conv-sat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
float-round-conv.ll [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn) 2022-01-11 09:05:57 -08:00
float-select-fcmp.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
flt-rounds.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
fmax-fmin.ll [SDAG] avoid libcalls to fmin/fmax for soft-float targets 2022-03-30 11:22:03 -04:00
fold-addi-loadstore.ll [RISCV] Fix a mistake in PostprocessISelDAG 2022-02-25 12:38:31 +00:00
fold-vector-cmp.ll [SelectionDAG] Use correct boolean representation in FoldConstantArithmetic 2022-04-28 18:42:16 +02:00
fp-imm.ll [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
fp16-promote.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
fp128.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
fpclamptosat.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
fpclamptosat_vec.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
fpenv.ll
…
frame-info.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
frame.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
frameaddr-returnaddr.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
frm-dependency.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll [RISCV] Add llvm.read.register support for vlenb 2022-05-13 09:12:02 -07:00
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
half-arith-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-arith.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
half-bitmanip-dagcombines.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-br-fcmp.ll [RISCV] Remove some TODOs in tests 2022-05-11 22:53:50 +08:00
half-convert-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-convert.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
half-fcmp-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-fcmp.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-frem.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-imm.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-intrinsics.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
half-isnan.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-mem.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
half-round-conv-sat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
half-round-conv.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-select-fcmp.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
hoist-global-addr-base.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
i32-icmp.ll [RISCV][NFC] Add immediate tests for the icmp instruction 2022-03-30 02:51:26 +00:00
i64-icmp.ll [RISCV] [NFC] Add Immediate tests for the cmov instruction 2022-04-06 03:08:55 +00:00
iabs.ll [LegalizeTypes][RISCV][WebAssembly] Expand ABS in PromoteIntRes_ABS if it will expand to sra+xor+sub later. 2022-03-15 08:27:39 -07:00
imm-cse.ll
…
imm.ll [RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW. 2022-04-29 08:58:32 -07:00
indirectbr.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
init-array.ll
…
inline-asm-S-constraint.ll [RISCV] Support machine constraint "S" 2021-07-13 09:30:09 -07:00
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. 2022-03-02 11:22:46 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. 2022-03-02 11:22:46 -08:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll [RISCV] Don't allow vector types to be used with inline asm 'r' constraint 2021-12-23 20:32:36 -06:00
inline-asm-zfh-constraint-f.ll [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. 2022-03-02 11:22:46 -08:00
inline-asm.ll [RISCV] Don't advertise i32->i64 zextload as free for RV64. 2022-01-06 08:13:42 -08:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
jumptable.ll [RISCV] Generate 32 bits jumptable entries when code model is small 2022-01-11 18:20:37 +08:00
large-stack.ll [RISCV] Merge addi into load/store as there is a ADD between them 2022-04-29 04:33:05 +00:00
legalize-fneg.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
lit.local.cfg
…
live-sp.mir [RISCV] Fix invalid kill on callee save 2021-11-02 11:56:54 +00:00
loop-strength-reduce-add-cheaper-than-mul.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
loop-strength-reduce-loop-invar.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
lsr-legaladdimm.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
machine-cse.ll [RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ. 2022-05-02 20:21:16 -07:00
machine-outliner-cfi.mir [RISCV] Precommit test for D122634 2022-04-22 12:19:55 +08:00
machine-outliner-patchable.ll [MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL 2021-12-13 13:24:29 -08:00
machine-outliner-position.mir [RISCV] Precommit test for D122634 2022-04-22 12:19:55 +08:00
machine-outliner-throw.ll [RISCV] Do not outline CFI instructions when they are needed in EH 2022-04-22 12:28:19 +08:00
machinelicm-address-pseudos.ll [RISCV] Ensure PseudoLA* can be hoisted 2022-03-16 18:45:36 +00:00
machineoutliner-jumptable.mir [RISCV] Fix Machine Outliner jump table handling. 2021-09-09 07:32:30 +02:00
machineoutliner.mir
…
make-compressible-rv64.mir [RISCV] Add pre-emit pass to make more instructions compressible 2022-05-25 09:25:02 +01:00
make-compressible.mir [RISCV] Add pre-emit pass to make more instructions compressible 2022-05-25 09:25:02 +01:00
mattr-invalid-combination.ll [RISCV] Remove check and update test file in D121183 2022-03-24 00:48:52 +08:00
mem.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
mem64.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
min-max.ll [DAGCombiner] Fold (sext/zext undef) -> 0 and aext(undef) -> undef. 2022-05-05 09:34:18 -07:00
mir-target-flags.ll [RISCV] Ensure PseudoLA* can be hoisted 2022-03-16 18:45:36 +00:00
module-target-abi.ll
…
module-target-abi2.ll [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute 2022-03-24 00:48:52 +08:00
mul.ll [DAG] try to convert multiply to shift via demanded bits 2022-02-23 12:09:32 -05:00
musttail-call.ll
…
neg-abs.ll [DAGCombiner] Don't expand (neg (abs x)) if the abs has an additional user. 2022-03-01 07:32:07 -08:00
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll [DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience 2021-12-23 10:48:28 +05:30
out-of-reach-emergency-slot.mir [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
overflow-intrinsic-optimizations.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
patchable-function-entry.ll Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" 2021-05-29 15:11:37 +01:00
pic-models.ll
…
pr40333.ll
…
pr51206.ll [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
pr53662.mir [RISCV] Don't getDebugLoc for the end node of MBB iterator 2022-04-30 16:00:20 +08:00
pr55201.ll [DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask. 2022-04-30 11:02:30 -07:00
prefetch.ll
…
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll Revert "[RISCV] Enable subregister liveness tracking for RVV." 2022-05-13 10:59:58 -07:00
rem.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
remat.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll [LegalizeTypes] Fix bug in expensive checks verification 2022-05-26 13:13:32 -07:00
rv32e.ll
…
rv32i-rv64i-float-double.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
rv32i-rv64i-half.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
rv32zba.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv32zbb-intrinsic.ll [RISCV] Add computeKnownBits support for RISCVISD::GORC. 2022-03-28 16:56:33 -07:00
rv32zbb-zbp-zbkb.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv32zbb.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv32zbc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbc-zbkc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbe-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbf-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbkb-intrinsic.ll [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV. 2022-01-30 12:41:09 -08:00
rv32zbkx-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbp-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbp-zbkb.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv32zbp.ll [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits 2022-05-14 09:50:01 +01:00
rv32zbr.ll
…
rv32zbs.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv32zbt-intrinsic.ll [RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW. 2022-03-05 21:26:51 -08:00
rv32zbt.ll [RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3). 2022-04-08 09:04:04 -07:00
rv32zknd-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zkne-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zknh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zksed-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zksh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64-large-stack.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
rv64d-double-convert-strict.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
rv64d-double-convert.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
rv64f-float-convert-strict.ll [RISCV] Support strict FP conversion operations. 2021-12-23 09:40:58 -06:00
rv64f-float-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64i-complex-float.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
rv64i-demanded-bits.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64i-double-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll [RISCV][NFC] Remove solved TODO for combining constant shifts 2022-05-26 09:55:19 +08:00
rv64i-single-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
rv64m-exhaustive-w-insts.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
rv64zba.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv64zbb-intrinsic.ll [RISCV] Add computeKnownBits support for RISCVISD::GORC. 2022-03-28 16:56:33 -07:00
rv64zbb-zbp-zbkb.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv64zbb.ll [RISCV] With Zbb, fold (sext_inreg (abs X)) -> (max X, (negw X)) 2022-03-03 15:42:29 -08:00
rv64zbc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbc-zbkc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbe-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbf-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbkb-intrinsic.ll [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV. 2022-01-30 12:41:09 -08:00
rv64zbkx-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbp-intrinsic.ll [RISCV] Add computeKnownBits support for RISCVISD::GORC. 2022-03-28 16:56:33 -07:00
rv64zbp-zbkb.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbp.ll [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits 2022-05-14 09:50:01 +01:00
rv64zbr.ll
…
rv64zbs.ll [RISCV][NFC] Simplify tests by reorganizing check prefixes 2022-05-12 02:22:56 +00:00
rv64zbt-intrinsic.ll [RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW. 2022-03-05 21:26:51 -08:00
rv64zbt.ll [RISCV] transform MI to W variant to remove sext.w 2022-04-22 10:59:26 -07:00
rv64zfh-half-convert-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zfh-half-convert.ll [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X). 2022-02-24 09:19:01 -08:00
rv64zfh-half-intrinsics-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zfh-half-intrinsics.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zknd-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zknd-zkne-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zkne-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zknh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zksed-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zksh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
sadd_sat.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
sadd_sat_plus.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
saverestore.ll
…
scalable-vector-struct.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll [RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y)) 2021-08-10 09:02:56 -07:00
select-cc.ll [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z) 2022-04-07 05:55:53 +00:00
select-const.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
select-constant-xor.ll [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range 2022-03-29 14:46:49 +08:00
select-optimize-multiple.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
select-optimize-multiple.mir [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
select-or.ll
…
selectcc-to-shiftand.ll [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases 2022-03-30 11:46:42 -07:00
setcc-logic.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
sext-zext-trunc.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
sextw-removal.ll [RISCV] transform MI to W variant to remove sext.w 2022-04-22 10:59:26 -07:00
shadowcallstack.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
shift-and.ll [RISCV] Add another isel optimization for (and (shl x, c2), c1) 2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
shifts.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
shlimm-addimm.ll [RISCV][test] Add tests of (add (shl r, c0), c1) 2021-10-14 14:53:03 +00:00
shrinkwrap.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
sink-icmp.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
spill-fpr-scalar.ll [RISCV] Add +experimental-zvfh extension to cover half types in vectors. 2022-03-17 10:04:02 -07:00
split-offsets.ll [DAGCombiner] reassociationCanBreakAddressingModePattern should check uses of the outer add. 2022-05-02 16:38:53 -07:00
split-sp-adjust.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
srem-lkk.ll [RISCV] Use constant pool for large integers 2021-12-31 14:48:48 +08:00
srem-seteq-illegal-types.ll [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits 2022-05-14 09:50:01 +01:00
srem-vector-lkk.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
ssub_sat.ll [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines 2022-04-13 10:01:07 +00:00
ssub_sat_plus.ll [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines 2022-04-13 10:01:07 +00:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
stack-realignment.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
stack-slot-size.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
stack-store-check.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
subtarget-features-std-ext.ll
…
switch-width.ll [riscv] Add a bunch of tests exploring switch lowering 2022-05-11 13:16:31 -07:00
tail-calls.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
uadd_sat.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
uadd_sat_plus.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
unaligned-load-store.ll [RISCV] Add a subtarget feature to enable unaligned scalar loads and stores 2022-05-26 15:25:47 -07:00
unfold-masked-merge-scalar-variablemask.ll [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines 2022-04-13 10:01:07 +00:00
unroll-loop-cse.ll Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
urem-lkk.ll [RISCV] Use constant pool for large integers 2021-12-31 14:48:48 +08:00
urem-seteq-illegal-types.ll [RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3). 2022-04-08 09:04:04 -07:00
urem-vector-lkk.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
usub_sat.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
usub_sat_plus.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
vadd-vp-mask.ll [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations 2022-04-26 02:30:22 +00:00
vararg.ll [RISCV] Add special case to constant materialization to remove trailing zeros first. 2022-04-21 09:43:32 -07:00
vec3-setcc-crash.ll [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits 2022-05-14 09:50:01 +01:00
vector-abi.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-instr.mir
…
vlenb.ll Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV) 2022-05-16 16:38:30 -07:00
vmul-vp-mask.ll [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations 2022-04-26 02:30:22 +00:00
vsub-vp-mask.ll [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations 2022-04-26 02:30:22 +00:00
wide-mem.ll
…
xaluo.ll [RISCV] Precommit test cases for (uaddo X, C) 2022-05-03 03:51:36 +00:00
zext-with-load-is-free.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
zfh-half-intrinsics-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
zfh-half-intrinsics.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
zfh-imm.ll [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00