Commit Graph

9667 Commits

Author SHA1 Message Date
Serge Pavlov ec893da990 [GlobalISel] Remove semantic operand of G_IS_FPCLASS
Instruction G_IS_FPCLASS had an operand that represented floating-point
semantics of its first operand. It allowed types that have the same length,
like `bfloat16` and `half`, to be distinguished. Unfortunately, it is
not sufficient, as other operation still cannot distinguish such types.
Solution of this problem must be more general, so now this operand is removed.

Differential Revision: https://reviews.llvm.org/D138004
2022-11-15 15:48:05 +07:00
Philip Reames 780c539844 [RISCV] Implement assembler support for XVentanaCondOps
This change provides an implementation of the XVentanaCondOps vendor extension. This extension is defined in version 1.0.0 of the VTx-family custom instructions specification (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems.

In addition to the technical contribution, this change is intended to be a test case for our vendor extension policy.

Once this lands, I plan to use this extension to prototype selection lowering to conditional moves. There's an RVI proposal in flight, and the expectation is that lowering to these and the new RVI instructions is likely to be substantially similar.

Differential Revision: https://reviews.llvm.org/D137350
2022-11-14 09:01:54 -08:00
Mindong Chen 9d78bbe6c4 [docs][OpaquePtr] Fix hyperlinks 2022-11-14 23:21:04 +08:00
Aiden Grossman b9378a60c4 [Docs] Add Documentation on BOLT Build Configs
This patch adds documentation into the advanced builds documentation on
how to use the BOLT caches, including the combinations with the PGO
multistage builds and (Thin)LTO.

Reviewed By: sylvestre.ledru, Amir

Differential Revision: https://reviews.llvm.org/D137899
2022-11-14 07:00:16 +00:00
Aiden Grossman f7dea68066 [Docs] Add Documentation on (Thin)LTO + PGO Build Configs
This patch adds documentation on the AdvancedBuilds page on how to do
PGO builds with (Thin)LTO with the currently undocumented (as far as I
can tell) PGO_INSTRUMENT_LTO option in the Clang PGO caches.

Reviewed By: sylvestre.ledru

Differential Revision: https://reviews.llvm.org/D137898
2022-11-14 06:58:00 +00:00
Aiden Grossman f53fde8e15 [Docs] Minor Fixups in Advanced Builds Documentation
This patch makes some minor fixups in the PGO section of the advanced
builds documentation in preparation for some future changes. Some minor
formatting and wording changes are included to hopefully make the
documentation more clear.

Reviewed By: sylvestre.ledru

Differential Revision: https://reviews.llvm.org/D137880
2022-11-12 22:03:25 +00:00
Tom Stellard b473734efd docs: add instructions for stand-alone builds of lld
Reviewed By: kwk, MaskRay

Differential Revision: https://reviews.llvm.org/D124405
2022-11-11 15:19:26 -08:00
Xiaodong Liu 070ab2bb0b [LangRef][LoongArch] Update inline asm constraint code and operand modifier
According to:
https://reviews.llvm.org/D134157
https://reviews.llvm.org/D136841
https://reviews.llvm.org/D136835

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D137528
2022-11-11 14:25:29 +08:00
Tom Stellard 1cb97a1e2d docs: Add instructions for stand-alone builds of clang
More sub-projects will be added to the table once they have been verified
to be buildable in stand-alone mode.

Reviewed By: MaskRay, mgorny

Differential Revision: https://reviews.llvm.org/D123968
2022-11-10 12:29:20 -08:00
Keith Walker 00d98e6572 [AArch64] RME MEC instructions and system registers
This patch adds assembler/disassembler support for
RME MEC (Memory Encryption Contexts).

Cache maintence instructions added:
- DC CIPAPA
- DC CIGDPAPA

System registers added:
- MECIDR_EL2
- MECID_P0_EL2
- MECID_A0_EL2
- MECID_P1_EL2
- MECID_A1_EL2
- VMECID_P_EL2
- VMECID_A_EL2
- MECID_RL_A_EL3

Differential Revision: https://reviews.llvm.org/D137431
2022-11-10 14:05:12 +00:00
Victor Campos 9d1ff787e5 [AArch64] Add support for the Cortex-X3 CPU
Cortex-X3 is an Armv9-A AArch64 CPU.

This patch introduces support for Cortex-X3.

Technical Reference Manual: https://developer.arm.com/documentation/101593/latest

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D136589
2022-11-09 11:33:48 +00:00
Freddy Ye 84a18a260e [X86] Support -march=sierraforest, grandridge, graniterapids.
Reviewed By: skan, pengfei, MaskRay

Differential Revision: https://reviews.llvm.org/D137153
2022-11-09 16:56:03 +08:00
Bjorn Pettersson ac696ac453 Use opt -passes=<name> instead of opt -name
Updated the RUN line in several test cases to use the new PM syntax
  opt -passes=<pipeline>
instead of the deprecated syntax
  opt -pass1 -pass2
2022-11-08 12:15:42 +01:00
Paulo Matos b293de9880 [Docs] Add my Office Hours 2022-11-07 22:02:07 -08:00
Fangrui Song 90ad3e3c02 [IR] Allow available_externally GlobalAlias
GlobalVariable and Function can be available_externally. GlobalAlias is used
similarly. Allowing available_externally is a natural extension and helps
ThinLTO discard GlobalAlias in a non-prevailing COMDAT (see D135427).

For now, available_externally GlobalAlias must point to an
available_externally GlobalValue (not ConstantExpr).

Differential Revision: https://reviews.llvm.org/D137441
2022-11-07 09:03:23 -08:00
Alexey Bader e0ed3d5d2e Online sync-ups: add SYCL working group sync details. 2022-11-06 08:16:36 -08:00
Nikita Popov 304f1d59ca [IR] Switch everything to use memory attribute
This switches everything to use the memory attribute proposed in
https://discourse.llvm.org/t/rfc-unify-memory-effect-attributes/65579.
The old argmemonly, inaccessiblememonly and inaccessiblemem_or_argmemonly
attributes are dropped. The readnone, readonly and writeonly attributes
are restricted to parameters only.

The old attributes are auto-upgraded both in bitcode and IR.
The bitcode upgrade is a policy requirement that has to be retained
indefinitely. The IR upgrade is mainly there so it's not necessary
to update all tests using memory attributes in this patch, which
is already large enough. We could drop that part after migrating
tests, or retain it longer term, to make it easier to import IR
from older LLVM versions.

High-level Function/CallBase APIs like doesNotAccessMemory() or
setDoesNotAccessMemory() are mapped transparently to the memory
attribute. Code that directly manipulates attributes (e.g. via
AttributeList) on the other hand needs to switch to working with
the memory attribute instead.

Differential Revision: https://reviews.llvm.org/D135780
2022-11-04 10:21:38 +01:00
Freddy Ye a806fc2767 [X86] Support -march=raptorlake, meteorlake
Reviewed By: pengfei, skan, MaskRay

Differential Revision: https://reviews.llvm.org/D135937
2022-11-04 09:32:17 +08:00
Simi Pallipurath fa8aeab606 [AArch64] Add support for the Cortex-A715 CPU
Cortex-A715 is an Armv9-A AArch64 CPU.

This patch introduces support for Cortex-A715.

Technical Reference Manual: https://developer.arm.com/documentation/101590/latest.

Reviewed By: vhscampos

Differential Revision: https://reviews.llvm.org/D136957
2022-11-03 09:28:46 +00:00
Matt Arsenault 5201680249 LangRef: Fix typo in backtick placement 2022-11-02 17:40:33 -07:00
Aaron Ballman 65b130e32c Fix LLVM sphinx build bot
This should address the issue found in:
https://lab.llvm.org/buildbot/#/builders/30/builds/27824
2022-11-02 14:33:39 -04:00
Arthur Eubanks 76b04c2beb [docs][NewPM] Move pass plugin documentation into existing new PM docs
Reviewed By: awarzynski, asbirlea

Differential Revision: https://reviews.llvm.org/D136626
2022-11-02 10:47:17 -07:00
Arthur Eubanks 5b30fc2369 [opt] Add -p alias for -passes
See [1] for background.

Some people have complained that `opt -passes=instcombine` is a lot more typing than `opt -instcombine`.
As a compromise that nobody has objected to in [1], allow `opt -p instcombine`.

[1] https://discourse.llvm.org/t/rfc-legacy-opt-pass-syntax-with-new-pass-manager/65863

Reviewed By: bjope, asbirlea

Differential Revision: https://reviews.llvm.org/D136616
2022-11-02 10:46:34 -07:00
Michał Górny c061892fcd [llvm-config] Remove --src-root option
Remove the `--src-root` option from the deprecated llvm-config tool.
None of the llvm-project projects use this option anymore. The value
was only meaningful for in-tree use and usually became no longer correct
once LLVM was installed -- either because it was built in a temporary
directory, or installed from a binary package and built on a different
system entirely.  Therefore, third-party tools could not have been
relying on it anyway.

The LLVM_SRC_ROOT #define is left intact, as it is used to compute
includedir when llvm-config is used in-source.

Differential Revision: https://reviews.llvm.org/D137144
2022-11-02 18:45:15 +01:00
OCHyams fcbf807b55 Fix Assignment Tracking docs error from 33c7ae55e7
Buildbot link: https://lab.llvm.org/buildbot/#/builders/30/builds/27812
2022-11-02 14:09:41 +00:00
OCHyams 33c7ae55e7 [Assignment Tracking][1/*] Add initial docs for Assignment Tracking
The Assignment Tracking debug-info feature is outlined in this RFC:

https://discourse.llvm.org/t/
  rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir

Add documentation outlining the intent and design.
2022-11-02 13:47:50 +00:00
Matt Arsenault da137e114e LangRef: Attempt to formulate some rules for addrspacecast
Some work will be needed to comply with these rules for non-integral
pointers.
2022-11-01 18:46:18 -07:00
Philip Reames 9395b98ba0 [RISCV][docs] Add some wording around vendor extensions
This adds an initial bit of policy around inclusion of vendor extensions. My intention here is to leave all of the actual decision making to a case by case decision on the regular sync calls, but to spell out some of the pieces we've discussed and (I think) have general agreement on.

Differential Revision: https://reviews.llvm.org/D136968
2022-11-01 09:33:32 -07:00
Yeting Kuo 71e4e35581 [VP][RISCV] Add vp.rint and RISC-V support.
FRINT uses dynamic rounding mode instead of static rounding mode. The patch
rename VFCVT_X_F_VL to VFCVT_RM_X_F_VL for static rounding mode uses and added
new ISDNode VFCVT_X_F_VL directly selected to PseudoVFCVT_X_F_V.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D136662
2022-11-01 14:52:47 +08:00
Patrick Walton 01859da84b [AliasAnalysis] Introduce getModRefInfoMask() as a generalization of pointsToConstantMemory().
The pointsToConstantMemory() method returns true only if the memory pointed to
by the memory location is globally invariant. However, the LLVM memory model
also has the semantic notion of *locally-invariant*: memory that is known to be
invariant for the life of the SSA value representing that pointer. The most
common example of this is a pointer argument that is marked readonly noalias,
which the Rust compiler frequently emits.

It'd be desirable for LLVM to treat locally-invariant memory the same way as
globally-invariant memory when it's safe to do so. This patch implements that,
by introducing the concept of a *ModRefInfo mask*. A ModRefInfo mask is a bound
on the Mod/Ref behavior of an instruction that writes to a memory location,
based on the knowledge that the memory is globally-constant memory (in which
case the mask is NoModRef) or locally-constant memory (in which case the mask
is Ref). ModRefInfo values for an instruction can be combined with the
ModRefInfo mask by simply using the & operator. Where appropriate, this patch
has modified uses of pointsToConstantMemory() to instead examine the mask.

The most notable optimization change I noticed with this patch is that now
redundant loads from readonly noalias pointers can be eliminated across calls,
even when the pointer is captured. Internally, before this patch,
AliasAnalysis was assigning Ref to reads from constant memory; now AA can
assign NoModRef, which is a tighter bound.

Differential Revision: https://reviews.llvm.org/D136659
2022-10-31 13:03:41 -07:00
Freddy Ye aee2a35ac4 [X86] Add AVX-NE-CONVERT instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D135930
2022-10-31 23:39:38 +08:00
Daniel Thornburgh cc2457ca1b [llvm-objdump] Set --print-imm-hex by default.
This was previously attempted in 2016 by colinl's D18770, but LLD tests
were missed, which caused the change to be reverted.

Setting --print-imm-hex by default brings llvm-objdump's behavior closer
in line with objdump, and it makes it easier to read addresses and
alignment from the disassembly. It may make non-address immediates
harder to interpret, but it still seems the better default, barring more
context-sensitive base selection logic.

Differential Revision: https://reviews.llvm.org/D136972
2022-10-30 13:36:18 -07:00
Arthur Eubanks 5404fe3456 Revert "[LegacyPM] Remove pipeline extension mechanism"
This reverts commit 4ea6ffb7e8.

Breaks various backends.
2022-10-28 10:26:58 -07:00
Arthur Eubanks 4ea6ffb7e8 [LegacyPM] Remove pipeline extension mechanism
Part of gradually removing the legacy PM optimization pipeline.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D136622
2022-10-28 10:16:52 -07:00
Craig Topper 974e2e690b [RISCV] Adjust RV64I data layout by using n32:64 in layout string
Although i32 type is illegal in the backend, RV64I has pretty good support for i32 types by using W instructions.

By adding n32 to the DataLayout string, middle end optimizations will consider i32 to be a native type. One known effect of this is enabling LoopStrengthReduce on loops with i32 induction variables. This can be beneficial because C/C++ code often has loops with i32 induction variables due to the use of `int` or `unsigned int`.

If this patch exposes performance issues, those are better addressed by tuning LSR or other passes.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D116735
2022-10-28 08:27:03 -07:00
Kadir Cetinkaya b999ac1af6
[llvm] Fix minimum Apple Clang requirement
This was stated as 9.3, but as pointed out in
https://discourse.llvm.org/t/rfc-bump-minimal-requirements-apple-clang-9-3-10-0-0-before-4th-tue-in-january/66156/7?u=kadircet
9.3 doesn't exist, hence this was effectively 10.0.

This patch merely reflects the reality more closely.

Differential Revision: https://reviews.llvm.org/D136609
2022-10-28 15:12:24 +02:00
Kristof Beyls f4a338ebf8 Online sync-ups: remove Windows/COFF entry.
They stopped a while ago.

Differential Revision: https://reviews.llvm.org/D136876
2022-10-28 14:48:02 +02:00
Freddy Ye 23f02693ec [X86] Add AVX-VNNI-INT8 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135938
2022-10-28 10:39:54 +08:00
Freddy Ye 0e720e6ada [X86] Add AVX-IFMA instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135932
2022-10-28 09:42:30 +08:00
Kristof Beyls 739b0df399 Community calendar: more clearly document how to add events 2022-10-27 21:15:01 +02:00
David Spickett c6e2de6042 [LLVM] Use DWARFv4 bitfields when tuning for GDB
GDB implemented data_bit_offset in https://sourceware.org/bugzilla/show_bug.cgi?id=12616
which has been present since GDB 8.0.

GCC started using it at GCC 11.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D135583
2022-10-27 08:51:07 +00:00
James Y Knight 5713c2959c Update "Writing a Backend" doc to use named operand matching.
This brings it in line with recommended practice after the
introduction of sub-operand naming in a538d1f13a, and the
deprecation of positional argument matching in 5351878ba1.
2022-10-26 14:06:07 -04:00
Piyou Chen 7d7940fd77 [RISCV] add svinval extension
1. Add the svinval extension support
2. Add the svinval Predicates for its instruction

Note: the svinval instructions defined in https://reviews.llvm.org/D117654

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136571
2022-10-26 09:45:30 -07:00
Michael Maitland 64d5aedd06 [TableGen] Add log bang operator
This patch adds base 2 logarithm that returns integer result. I initially wanted to name it `!log2`,
but numbers are not permitted in the name. The documentation makes sure to clarify that it is
base 2 since it is not explicit in the operator name.

Differential Revision: https://reviews.llvm.org/D134068
2022-10-26 09:16:32 -07:00
Johannes Doerfert 8ce5dee74b
[Docs][NFC] Update my office hour information 2022-10-26 08:14:54 -07:00
Freddy Ye fdac4c4e92 [X86] Add CMPCCXADD instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135933
2022-10-25 14:33:39 +08:00
zhijian 1c84831fea [XCOFF] llvm-readobj support decoding the loader section header field for XCOFF object file.
Reviewers: James Henderson, Esme Yi

Differential Revision: https://reviews.llvm.org/D134883
2022-10-24 13:31:01 -04:00
Xiang1 Zhang 661881d436 [X86] Add AMX-FP16 instructions.
Differential Revision: https://reviews.llvm.org/D135941
2022-10-22 08:05:22 +08:00
Nikita Popov 9d9de5a5df [LangRef] Add memory attribute
This adds the LangRef wording for the memory attribute proposed at
https://discourse.llvm.org/t/rfc-unify-memory-effect-attributes/65579.

The old attributes are not removed from LangRef until the migration
is finished.

Differential Revision: https://reviews.llvm.org/D135597
2022-10-21 12:11:25 +02:00
Quentin Colombet d7aba027af [docs] Add myself for LLVM Office hours
Add an entry for my office hours. Intended focus is low-level LLVM
stuff.

Differential Version: https://reviews.llvm.org/D136270
2022-10-19 18:25:21 +00:00