Revert "[VENTUS][fix] Add subregclass and flag to distinguish GPR and GPRF32" (#68)

This reverts commit 5e424e2b64.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -185,6 +185,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (RISCV::GPRF32RegClass.contains(SrcReg) &&
       RISCV::VGPRRegClass.contains(DstReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::VFMV_S_F), DstReg)
+        .addReg(DstReg, RegState::Undef)
         .addReg(SrcReg, getKillRegState(KillSrc));
     return;
   }
@@ -243,10 +244,6 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     Opcode = RISCV::FSW;
   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSD;
-  } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
-    Opcode = RISCV::FSW;
-  } else if (RISCV::GPRF64RegClass.hasSubClassEq(RC)) {
-    Opcode = RISCV::FSD;
   } else if (RISCV::VGPRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VSW;
   } else
@@ -290,10 +287,6 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     Opcode = RISCV::FLW;
   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FLD;
-  } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
-    Opcode = RISCV::FLW;
-  } else if (RISCV::GPRF64RegClass.hasSubClassEq(RC)) {
-    Opcode = RISCV::FLD;
   } else if (RISCV::VGPRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VLW;
   } else

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -216,8 +216,6 @@ RISCVRegisterInfo::getPhysRegClass(MCRegister Reg) const {
     */
     &RISCV::VGPRRegClass,
     &RISCV::GPRRegClass,
-    &RISCV::GPRF32RegClass,
-    &RISCV::GPRF64RegClass,
   };
 
   for (const TargetRegisterClass *BaseClass : BaseClasses) {

llvm/lib/Target/RISCV/VentusRegisterInfo.td

@@ -32,11 +32,9 @@ class RVRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
   // vALU and sALU registers
   field bit IsVGPR = 0;
   field bit IsSGPR = 0;
-  field bit IsFGPR = 0;
 
   let TSFlags{0} = IsVGPR;
   let TSFlags{1} = IsSGPR;
-  let TSFlags{2} = IsFGPR;
 }
 
 class RISCVReg<bits<8> Enc, string n, list<string> alt = []> : Register<n> {
@@ -242,29 +240,6 @@ let RegAltNameIndices = [ABIRegAltName] in {
   }
 }
 
-// Float registers
-let RegAltNameIndices = [ABIRegAltName] in {
-  let CostPerUse = [0, 1] in {
-    foreach Index = {5, 6, 7, 16...63} in {
-      defvar Reg = !cast<Register>("X"#Index);
-      def F#Index#SUB : RISCVRegWithSubRegs<Index, Reg.AsmName,
-                                            [!cast<Register>("X"#Index)],
-                                            Reg.AltNames> {
-        let SubRegIndices = [lo32];
-      }
-    }
-  }
-
-  foreach Index = [8, 9, 11, 12, 13, 14, 15] in {
-    defvar Reg = !cast<Register>("X"#Index);
-    def F#Index#SUB : RISCVRegWithSubRegs<Index, Reg.AsmName,
-                                          [!cast<Register>("X"#Index)],
-                                          Reg.AltNames> {
-      let SubRegIndices = [lo32];
-    }
-  }
-}
-
 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
                                [i32,  i64]>;
 def XLenRI : RegInfoByHwMode<
@@ -281,14 +256,6 @@ def GPR : RVRegisterClass<"RISCV", [XLenVT], 32, (add
   let IsSGPR = 1;
 }
 
-def FPRSUB : RVRegisterClass<"RISCV", [f32], 32, (add
-    (sequence "F%uSUB", 5, 9),
-    (sequence "F%uSUB", 11, 63)
-  )> {
-  let RegInfos = XLenRI;
-  let IsFGPR = 1;
-}
-
 def GPRX0 : RVRegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
   let RegInfos = XLenRI;
   let IsSGPR = 1;
@@ -449,9 +416,9 @@ def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
 }
 
 let RegInfos = XLenRI in {
-def GPRF16  : RegisterClass<"RISCV", [f16], 16, (add FPRSUB)>;
+def GPRF16  : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
-def GPRF32  : RegisterClass<"RISCV", [f32], 32, (add FPRSUB)>;
+def GPRF32  : RegisterClass<"RISCV", [f32], 32, (add GPR)>;
-def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add FPRSUB)>;
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
 } // RegInfos = XLenRI
 
 let RegAltNameIndices = [ABIRegAltName] in {