From f5df45650fd1e80e3fc3377e5152a50fc6090635 Mon Sep 17 00:00:00 2001
From: yanming <ming.yan@terapines.com>
Date: Fri, 7 Jul 2023 11:12:24 +0800
Subject: [PATCH] [VENTUS][RISCV] Fix private memory load/store instructions
 definitions.

---
 llvm/lib/Target/RISCV/VentusInstrFormatsV.td | 23 --------------------
 llvm/lib/Target/RISCV/VentusInstrInfoV.td    | 23 +++++++++++---------
 2 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/llvm/lib/Target/RISCV/VentusInstrFormatsV.td b/llvm/lib/Target/RISCV/VentusInstrFormatsV.td
index 854ef0011366..c2ba617a1077 100644
--- a/llvm/lib/Target/RISCV/VentusInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/VentusInstrFormatsV.td
@@ -62,29 +62,6 @@ class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
   let Opcode = OPC_OP_V.Value;
 }
 
-// vsetvli inst format is used by private memory loads VLW/VLH/VLB
-class RVInstSetVLVLi<dag outs, dag ins, string opcodestr, string argstr>
-    : RVInstSetVLi<outs, ins, opcodestr, argstr> {
-  bits<5> vd;
-  bits<11> imm11;
-
-  let Inst{31} = 1;
-  let Inst{30-20} = imm11;
-  let Inst{11-7} = vd;
-}
-
-// vsetvli inst format is used by private memory stores VSW/VSH/VSB
-class RVInstSetVSVLi<dag outs, dag ins, string opcodestr, string argstr>
-    : RVInstSetVLi<outs, ins, opcodestr, argstr> {
-  bits<5> vd;
-  bits<11> imm11;
-
-  let Inst{31} = 0;
-  let Inst{30-25} = imm11{10-5};
-  let Inst{24-20} = vd;
-  let Inst{11-7} = imm11{4-0};
-}
-
 class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
diff --git a/llvm/lib/Target/RISCV/VentusInstrInfoV.td b/llvm/lib/Target/RISCV/VentusInstrInfoV.td
index ac51fbf702da..41215de453a7 100644
--- a/llvm/lib/Target/RISCV/VentusInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/VentusInstrInfoV.td
@@ -683,17 +683,20 @@ class Branch_i<bits<3> funct3, string opcodestr>
 }
 
 // Private memory load/store instructions
-class VENTUS_VL<bits<3> funct3, string opcodestr>:
-          RVInstSetVLVLi<(outs VGPR:$vd), (ins VGPRMem:$vs1, simm11:$imm11),
-                      opcodestr # ".v", "$vd, ${imm11}(${vs1})"> {
-      let Inst{14-12} = funct3;
-      let Opcode = OPC_CUSTOM_1.Value;
+class VENTUS_VL<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_V, (outs VGPR:$rd),
+              (ins VGPRMem:$rs1, simm11:$imm12),
+              opcodestr # ".v", "$rd, ${imm12}(${rs1})"> {
+  let Inst{31} = 0;
+  let Inst{30-20} = imm12{10-0};
 }
-class VENTUS_VS<bits<3> funct3, string opcodestr>:
-          RVInstSetVSVLi<(outs), (ins VGPR:$vd, VGPRMem:$vs1, simm11:$imm11),
-                      opcodestr # ".v", "$vd, ${imm11}(${vs1})"> {
-      let Inst{14-12} = funct3;
-      let Opcode = OPC_CUSTOM_1.Value;
+class VENTUS_VS<bits<3> funct3, string opcodestr>
+    : RVInstS<funct3, OPC_OP_V, (outs),
+              (ins VGPR:$rs2, VGPRMem:$rs1, simm11:$imm12),
+              opcodestr # ".v", "$rs2, ${imm12}(${rs1})"> {
+  let Inst{31} = 1;
+  let Inst{30-25} = imm12{10-5};
+  let Inst{11-7} = imm12{4-0};
 }
 
 // Local/Global memory load/store instructions