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[RISCV] Merge ReplaceNodeResults code for SHFL and GREV/GORC. NFC

This commit is contained in:
Craig Topper 2022-03-13 13:57:43 -07:00
parent ec06edc6fa
commit eeb3bfd74a
1 changed files with 2 additions and 16 deletions
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18
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -6816,7 +6816,8 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
break;
}
case RISCVISD::GREV:
case RISCVISD::GORC: {
case RISCVISD::GORC:
case RISCVISD::SHFL: {
MVT VT = N->getSimpleValueType(0);
MVT XLenVT = Subtarget.getXLenVT();
assert((VT == MVT::i16 || (VT == MVT::i32 && Subtarget.is64Bit())) &&
@ -6835,21 +6836,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NewRes));
break;
}
case RISCVISD::SHFL: {
// There is no SHFLIW instruction, but we can just promote the operation.
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
assert(isa<ConstantSDNode>(N->getOperand(1)) && "Expected constant");
SDValue NewOp0 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
SDValue NewOp1 =
DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1));
SDValue NewRes = DAG.getNode(RISCVISD::SHFL, DL, MVT::i64, NewOp0, NewOp1);
// ReplaceNodeResults requires we maintain the same type for the return
// value.
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes));
break;
}
case ISD::BSWAP:
case ISD::BITREVERSE: {
MVT VT = N->getSimpleValueType(0);