Merge pull request #101 from THU-DSP-LAB/resource_manage

[VENTUS][fix] Fix ventus resource usage calculation error

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -549,10 +549,6 @@ public:
     return false;
   }
 
-  /// Analyze register usage information
-  virtual void analyzeRegisterUsage(DenseSet<llvm::Register> RewriteRegs,
-                                      MachineFunction *MF) const {}
-
   /// Returns true if PhysReg is unallocatable and constant throughout the
   /// function.  Used by MachineRegisterInfo::isConstantPhysReg().
   virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }

llvm/lib/CodeGen/VirtRegMap.cpp

@@ -639,7 +639,7 @@ void VirtRegRewriter::rewrite() {
       }
     }
   }
-  TRI->analyzeRegisterUsage(RewriteRegs, MF);
+
   RewriteRegs.clear();
 }
 

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

@@ -578,6 +578,43 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
                           getStackOffset(MF, FI, (RISCVStackID::Value)StackID));
 }
 
+void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
+  MachineFunction &MF,
+  RegScavenger *RS) const {
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+  auto *CurrentProgramInfo = const_cast<VentusProgramInfo*>(
+                    MF.getSubtarget<RISCVSubtarget>().getVentusProgramInfo());
+
+  // When accessing a new function, we need to add a new container to calculate 
+  // its resource usage.
+  CurrentProgramInfo->RegisterAddedSetVec.push_back(DenseSet<unsigned>());
+  CurrentProgramInfo->SubProgramInfoVec.push_back(SubVentusProgramInfo());
+
+  // Gets the container for the resource calculation of the current function.
+  auto *CurrentRegisterAddedSet = const_cast<DenseSet<unsigned>*>(
+                    MF.getSubtarget<RISCVSubtarget>().getCurrentRegisterAddedSet());
+  auto *CurrentSubProgramInfo = const_cast<SubVentusProgramInfo*>(
+                    MF.getSubtarget<RISCVSubtarget>().getCurrentSubProgramInfo());
+
+  for (auto &MBB : MF) {
+    for (auto &MI : MBB) {
+      for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
+        MachineOperand &Op = MI.getOperand(i);
+        if (!Op.isReg())
+          continue;
+
+        RI->insertRegToSet(MRI, CurrentRegisterAddedSet, 
+                    CurrentSubProgramInfo, Op.getReg());
+      }
+    }
+  }
+
+  // ra register is a special register.
+  RI->insertRegToSet(MRI, CurrentRegisterAddedSet, 
+                    CurrentSubProgramInfo, RISCV::X1);
+}
+
 void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                               BitVector &SavedRegs,
                                               RegScavenger *RS) const {

llvm/lib/Target/RISCV/RISCVFrameLowering.h

@@ -35,6 +35,10 @@ public:
   StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
                                      Register &FrameReg) const override;
 
+  void processFunctionBeforeFrameFinalized(
+    MachineFunction &MF,
+    RegScavenger *RS = nullptr) const override;
+
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
 

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -170,33 +170,6 @@ MCRegister RISCVRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
   return MCRegister();
 }
 
-void RISCVRegisterInfo::analyzeRegisterUsage(DenseSet<Register> RewriteRegs,
-                                      MachineFunction *MF) const  {
-  auto *CurrentProgramInfo = const_cast<VentusProgramInfo*>(
-                    MF->getSubtarget<RISCVSubtarget>().getVentusProgramInfo());
-
-  // When accessing a new function, we need to add a new container to calculate 
-  // its resource usage.
-  CurrentProgramInfo->RegisterAddedSetVec.push_back(DenseSet<unsigned>());
-  CurrentProgramInfo->SubProgramInfoVec.push_back(SubVentusProgramInfo());
-
-  // Gets the container for the resource calculation of the current function.
-  auto *CurrentRegisterAddedSet = const_cast<DenseSet<unsigned>*>(
-                    MF->getSubtarget<RISCVSubtarget>().getCurrentRegisterAddedSet());
-  auto *CurrentSubProgramInfo = const_cast<SubVentusProgramInfo*>(
-                    MF->getSubtarget<RISCVSubtarget>().getCurrentSubProgramInfo());
-  
-  const MachineRegisterInfo &MRI = MF->getRegInfo();
-
-  for(auto Reg : RewriteRegs) 
-    insertRegToSet(MRI, CurrentRegisterAddedSet, 
-                    CurrentSubProgramInfo, Reg);
-  
-  // ra register is a special register.
-  insertRegToSet(MRI, CurrentRegisterAddedSet, 
-                    CurrentSubProgramInfo, RISCV::X1);
-}
-
 bool RISCVRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
                                   Register Reg) const {
   const TargetRegisterClass *RC;
@@ -214,6 +187,10 @@ void RISCVRegisterInfo::insertRegToSet(const MachineRegisterInfo &MRI,
   if (CurrentRegisterAddedSet->contains(Reg))
     return;
 
+  // Beyond the limits of SGPR and VGPR
+  if (Reg.id() < RISCV::V0 || Reg.id() > RISCV::X63)
+    return;
+
   CurrentRegisterAddedSet->insert(Reg);
 
   if (!isSGPRReg(MRI, Reg)) 

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

@@ -138,8 +138,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
                                 const MachineFunction &MF,
                                 bool ReserveHighestVGPR = false) const;
 
-  void analyzeRegisterUsage(DenseSet<llvm::Register> RewriteRegs,
-                                      MachineFunction *MF) const override;
   unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
 
   bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,

llvm/test/CodeGen/RISCV/VentusGPGPU/resource-usage.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs  -asm-verbose < %s \
+; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs -O0 \
-; RUN:   | FileCheck -check-prefix=VENTUS %s
+; RUN: -asm-verbose < %s | FileCheck -check-prefix=VENTUS %s
 
 ; VENTUS: .section	.rodata.ventus.resource,"w",@progbits
 ; VENTUS: .half	2
@@ -11,14 +11,16 @@ define dso_local ventus_kernel void @usage(ptr addrspace(1) nocapture noundef al
 ; VENTUS-LABEL: usage:
 ; VENTUS:       # %bb.0: # %entry
 ; VENTUS-NEXT:    addi sp, sp, 4
-; VENTUS-NEXT:    sw ra, 0(sp) # 4-byte Folded Spill
+; VENTUS-NEXT:    sw ra, -4(sp) # 4-byte Folded Spill
-; VENTUS-NEXT:    lw t0, 4(a0)
 ; VENTUS-NEXT:    lw t1, 0(a0)
-; VENTUS-NEXT:    lw t0, 0(t0)
+; VENTUS-NEXT:    lw t0, 4(a0)
-; VENTUS-NEXT:    lw t2, 0(t1)
+; VENTUS-NEXT:    # kill: def $v0 killed $x5
-; VENTUS-NEXT:    add t0, t2, t0
+; VENTUS-NEXT:    # kill: def $v0 killed $x6
+; VENTUS-NEXT:    lw t2, 0(t0)
+; VENTUS-NEXT:    lw t0, 0(t1)
+; VENTUS-NEXT:    add t0, t0, t2
 ; VENTUS-NEXT:    sw t0, 0(t1)
-; VENTUS-NEXT:    lw ra, 0(sp) # 4-byte Folded Reload
+; VENTUS-NEXT:    lw ra, -4(sp) # 4-byte Folded Reload
 ; VENTUS-NEXT:    addi sp, sp, -4
 ; VENTUS-NEXT:    ret
 entry: