diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 2fadd5b4572c..36388089002c 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -549,10 +549,6 @@ public: return false; } - /// Analyze register usage information - virtual void analyzeRegisterUsage(DenseSet RewriteRegs, - MachineFunction *MF) const {} - /// Returns true if PhysReg is unallocatable and constant throughout the /// function. Used by MachineRegisterInfo::isConstantPhysReg(). virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; } diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 64af503421fc..069aca742da0 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -639,7 +639,7 @@ void VirtRegRewriter::rewrite() { } } } - TRI->analyzeRegisterUsage(RewriteRegs, MF); + RewriteRegs.clear(); } diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 40500f0cb556..712d4a59e6fb 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -578,6 +578,43 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, getStackOffset(MF, FI, (RISCVStackID::Value)StackID)); } +void RISCVFrameLowering::processFunctionBeforeFrameFinalized( + MachineFunction &MF, + RegScavenger *RS) const { + const MachineRegisterInfo &MRI = MF.getRegInfo(); + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + auto *CurrentProgramInfo = const_cast( + MF.getSubtarget().getVentusProgramInfo()); + + // When accessing a new function, we need to add a new container to calculate + // its resource usage. + CurrentProgramInfo->RegisterAddedSetVec.push_back(DenseSet()); + CurrentProgramInfo->SubProgramInfoVec.push_back(SubVentusProgramInfo()); + + // Gets the container for the resource calculation of the current function. + auto *CurrentRegisterAddedSet = const_cast*>( + MF.getSubtarget().getCurrentRegisterAddedSet()); + auto *CurrentSubProgramInfo = const_cast( + MF.getSubtarget().getCurrentSubProgramInfo()); + + for (auto &MBB : MF) { + for (auto &MI : MBB) { + for (unsigned i = 0; i < MI.getNumOperands(); ++i) { + MachineOperand &Op = MI.getOperand(i); + if (!Op.isReg()) + continue; + + RI->insertRegToSet(MRI, CurrentRegisterAddedSet, + CurrentSubProgramInfo, Op.getReg()); + } + } + } + + // ra register is a special register. + RI->insertRegToSet(MRI, CurrentRegisterAddedSet, + CurrentSubProgramInfo, RISCV::X1); +} + void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index f3e69c844079..42252731d0c1 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -35,6 +35,10 @@ public: StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override; + void processFunctionBeforeFrameFinalized( + MachineFunction &MF, + RegScavenger *RS = nullptr) const override; + void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override; diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 0854bb742b2b..c8c5a1c06b7e 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -170,33 +170,6 @@ MCRegister RISCVRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI, return MCRegister(); } -void RISCVRegisterInfo::analyzeRegisterUsage(DenseSet RewriteRegs, - MachineFunction *MF) const { - auto *CurrentProgramInfo = const_cast( - MF->getSubtarget().getVentusProgramInfo()); - - // When accessing a new function, we need to add a new container to calculate - // its resource usage. - CurrentProgramInfo->RegisterAddedSetVec.push_back(DenseSet()); - CurrentProgramInfo->SubProgramInfoVec.push_back(SubVentusProgramInfo()); - - // Gets the container for the resource calculation of the current function. - auto *CurrentRegisterAddedSet = const_cast*>( - MF->getSubtarget().getCurrentRegisterAddedSet()); - auto *CurrentSubProgramInfo = const_cast( - MF->getSubtarget().getCurrentSubProgramInfo()); - - const MachineRegisterInfo &MRI = MF->getRegInfo(); - - for(auto Reg : RewriteRegs) - insertRegToSet(MRI, CurrentRegisterAddedSet, - CurrentSubProgramInfo, Reg); - - // ra register is a special register. - insertRegToSet(MRI, CurrentRegisterAddedSet, - CurrentSubProgramInfo, RISCV::X1); -} - bool RISCVRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const { const TargetRegisterClass *RC; @@ -214,6 +187,10 @@ void RISCVRegisterInfo::insertRegToSet(const MachineRegisterInfo &MRI, if (CurrentRegisterAddedSet->contains(Reg)) return; + // Beyond the limits of SGPR and VGPR + if (Reg.id() < RISCV::V0 || Reg.id() > RISCV::X63) + return; + CurrentRegisterAddedSet->insert(Reg); if (!isSGPRReg(MRI, Reg)) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h index b1ce3a24812f..ad4f0d67d761 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -138,8 +138,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo { const MachineFunction &MF, bool ReserveHighestVGPR = false) const; - void analyzeRegisterUsage(DenseSet RewriteRegs, - MachineFunction *MF) const override; unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override; bool getRegAllocationHints(Register VirtReg, ArrayRef Order, diff --git a/llvm/test/CodeGen/RISCV/VentusGPGPU/resource-usage.ll b/llvm/test/CodeGen/RISCV/VentusGPGPU/resource-usage.ll index 4705bce7008d..ecfe59898e04 100644 --- a/llvm/test/CodeGen/RISCV/VentusGPGPU/resource-usage.ll +++ b/llvm/test/CodeGen/RISCV/VentusGPGPU/resource-usage.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs -asm-verbose < %s \ -; RUN: | FileCheck -check-prefix=VENTUS %s +; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs -O0 \ +; RUN: -asm-verbose < %s | FileCheck -check-prefix=VENTUS %s ; VENTUS: .section .rodata.ventus.resource,"w",@progbits ; VENTUS: .half 2 @@ -11,14 +11,16 @@ define dso_local ventus_kernel void @usage(ptr addrspace(1) nocapture noundef al ; VENTUS-LABEL: usage: ; VENTUS: # %bb.0: # %entry ; VENTUS-NEXT: addi sp, sp, 4 -; VENTUS-NEXT: sw ra, 0(sp) # 4-byte Folded Spill -; VENTUS-NEXT: lw t0, 4(a0) +; VENTUS-NEXT: sw ra, -4(sp) # 4-byte Folded Spill ; VENTUS-NEXT: lw t1, 0(a0) -; VENTUS-NEXT: lw t0, 0(t0) -; VENTUS-NEXT: lw t2, 0(t1) -; VENTUS-NEXT: add t0, t2, t0 +; VENTUS-NEXT: lw t0, 4(a0) +; VENTUS-NEXT: # kill: def $v0 killed $x5 +; VENTUS-NEXT: # kill: def $v0 killed $x6 +; VENTUS-NEXT: lw t2, 0(t0) +; VENTUS-NEXT: lw t0, 0(t1) +; VENTUS-NEXT: add t0, t0, t2 ; VENTUS-NEXT: sw t0, 0(t1) -; VENTUS-NEXT: lw ra, 0(sp) # 4-byte Folded Reload +; VENTUS-NEXT: lw ra, -4(sp) # 4-byte Folded Reload ; VENTUS-NEXT: addi sp, sp, -4 ; VENTUS-NEXT: ret entry: