From 4c099fb3d5fa542f446a93ef7ed36a59daa8d38b Mon Sep 17 00:00:00 2001
From: yanming <ming.yan@terapines.com>
Date: Fri, 7 Jul 2023 17:19:56 +0800
Subject: [PATCH] [VENTUS][RISCV] Move `regext insertion pass` after `insert
 join instruction pass`.

---
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp        | 2 +-
 llvm/test/CodeGen/RISCV/VentusGPGPU/vbranch-join.ll | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 86dfd5952b27..2ce9783ac6b1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -271,12 +271,12 @@ bool RISCVPassConfig::addGlobalInstructionSelect() {
 void RISCVPassConfig::addPreSched2() {}
 
 void RISCVPassConfig::addPreEmitPass() {
+  addPass(createVentusInsertJoinToVBranchPass());
   // NOTE: This pass must be at the end of all optimization passes, as it
   // breaks the def-use chain!
   // Insert regext instruction for instruction whose register id is greater
   // than 31.
   addPass(createVentusRegextInsertionPass());
-  addPass(createVentusInsertJoinToVBranchPass());
   addPass(&BranchRelaxationPassID);
   addPass(createRISCVMakeCompressibleOptPass());
 }
diff --git a/llvm/test/CodeGen/RISCV/VentusGPGPU/vbranch-join.ll b/llvm/test/CodeGen/RISCV/VentusGPGPU/vbranch-join.ll
index 9c35879e2f39..264a896fb4ac 100644
--- a/llvm/test/CodeGen/RISCV/VentusGPGPU/vbranch-join.ll
+++ b/llvm/test/CodeGen/RISCV/VentusGPGPU/vbranch-join.ll
@@ -143,27 +143,27 @@ define dso_local i32 @branch_in_branch(i32 noundef %dim) local_unnamed_addr {
 ; VENTUS-NEXT:    li t1, 14
 ; VENTUS-NEXT:    vmv.v.x v1, t1
 ; VENTUS-NEXT:    vmv.v.x v0, t0
-; VENTUS-NEXT:    regext zero, zero, 8
 ; VENTUS-NEXT:  .Lpcrel_hi4:
 ; VENTUS-NEXT:    auipc t1, %pcrel_hi(.LBB2_7)
 ; VENTUS-NEXT:    setrpc zero, t1, %pcrel_lo(.Lpcrel_hi4)
+; VENTUS-NEXT:    regext zero, zero, 8
 ; VENTUS-NEXT:    vblt v33, v1, .LBB2_7
 ; VENTUS-NEXT:  # %bb.1: # %if.else
 ; VENTUS-NEXT:    li t0, 17
 ; VENTUS-NEXT:    vmv.v.x v0, t0
-; VENTUS-NEXT:    regext zero, zero, 64
 ; VENTUS-NEXT:  .Lpcrel_hi5:
 ; VENTUS-NEXT:    auipc t1, %pcrel_hi(.LBB2_7)
 ; VENTUS-NEXT:    setrpc zero, t1, %pcrel_lo(.Lpcrel_hi5)
+; VENTUS-NEXT:    regext zero, zero, 64
 ; VENTUS-NEXT:    vbltu v0, v33, .LBB2_4
 ; VENTUS-NEXT:  # %bb.2: # %if.then2
 ; VENTUS-NEXT:    li t0, 1
 ; VENTUS-NEXT:    vmv.v.x v0, t0
 ; VENTUS-NEXT:    call _Z13get_global_idj
-; VENTUS-NEXT:    regext zero, zero, 64
 ; VENTUS-NEXT:  .Lpcrel_hi6:
 ; VENTUS-NEXT:    auipc t1, %pcrel_hi(.LBB2_6)
 ; VENTUS-NEXT:    setrpc zero, t1, %pcrel_lo(.Lpcrel_hi6)
+; VENTUS-NEXT:    regext zero, zero, 64
 ; VENTUS-NEXT:    vblt v0, v33, .LBB2_5
 ; VENTUS-NEXT:  # %bb.3: # %if.then2
 ; VENTUS-NEXT:    li t0, 23