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Merge pull request #112 from ziliangzl/Pseudo-FLW/FSW 

[VENTUS][fix] Fix FLW/FSW instruction encoding conflict
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zhoujingya 2024-04-26 13:28:05 +08:00 committed by GitHub
parent 968f0c07cd 8be3150696
commit 45856f653d
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2 changed files with 31 additions and 31 deletions
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56
llvm/lib/Target/RISCV/VentusInstrInfoF.td
View File

@ -340,29 +340,7 @@ class PseudoVFROUND<RegisterClass Ty>
// Instructions
//===----------------------------------------------------------------------===//
// FIXME: Ventus doesn't have FLW/FSW,it is same opcode with LW/SW
// but for GPRF32.
let Predicates = [HasStdExtZfinx] in {
/// Loads
def FLW : RVInstI<0b010, OPC_LOAD, (outs GPRF32:$rd),
(ins GPRMem:$rs1, simm12:$imm12),
"flw", "$rd, ${imm12}(${rs1})">,
Sched<[WriteLDW, ReadMemBase]>;
def : Pat<(f32 (UniformLoadFrag<load>
(AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
(FLW GPR:$rs1, simm12:$imm12)>;
/// Stores
def FSW : RVInstS<0b010, OPC_STORE, (outs),
(ins GPRF32:$rs2, GPRMem:$rs1, simm12:$imm12),
"fsw", "$rs2, ${imm12}(${rs1})">,
Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
def : Pat<(UniformStoreFrag<store> (f32 GPRF32:$rs2),
(AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
(FSW GPRF32:$rs2, GPR:$rs1, simm12:$imm12)>;
} // Predicates = [HasStdExtZfinx]
let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
defm FMADD_S : FPFMA_rrr_frm_m<OPC_MADD, 0b00, "fmadd.s", FINX>;
@ -466,8 +444,12 @@ defm : FPUnaryOpDynFrmAlias_m<FCVT_S_LU, "fcvt.s.lu", FXIN64X>;
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZfinx] in {
// def : InstAlias<"flw $rd, (${rs1})", (FLW GPRF32:$rd, GPR:$rs1, 0), 0>;
// def : InstAlias<"fsw $rs2, (${rs1})", (FSW GPRF32:$rs2, GPR:$rs1, 0), 0>;
// def : InstAlias<"flw $rd, ${imm12}(${rs1})",
// (LW GPR:$rd, GPR:$rs1, simm12:$imm12)>;
// def : InstAlias<"fsw $rs2, ${imm12}(${rs1})",
// (SW GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>;
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>;
@ -510,8 +492,26 @@ def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, ui
def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
def PseudoFLW : PseudoFloatLoad<"flw", GPRF32>;
def PseudoFSW : PseudoStore<"fsw", GPRF32>;
def PseudoFLW : Pseudo<(outs GPRF32:$rd), (ins GPRMem:$rs1, simm12:$imm12), [],
"flw", "$rd, ${imm12}(${rs1})">,
PseudoInstExpansion<(LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)> {
let hasSideEffects = 0;
let mayLoad = 1;
let mayStore = 0;
let isCodeGenOnly = 0;
let isAsmParserOnly = 1;
}
def PseudoFSW : Pseudo<(outs), (ins GPRF32:$rs2, GPRMem:$rs1, simm12:$imm12),
[], "fsw", "$rs2, ${imm12}(${rs1})">,
PseudoInstExpansion<(SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)> {
let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 1;
let isCodeGenOnly = 0;
let isAsmParserOnly = 1;
}
let usesCustomInserter = 1 in {
def PseudoQuietFLE_S : PseudoQuietFCMP<GPRF32>;
def PseudoQuietFLT_S : PseudoQuietFCMP<GPRF32>;
@ -654,11 +654,11 @@ def PseudoFROUND_S : PseudoFROUND<GPRF32>;
// /// Loads
// defm : UniformLdPat<load, FLW, f32>;
defm : UniformLdPat<load, PseudoFLW, f32>;
// /// Stores
// defm : UniformStPat<store, FSW, GPRF32, f32>;
defm : UniformStPat<store, PseudoFSW, GPRF32, f32>;
} // Predicates = [HasStdExtZfinx]

6
llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll
View File

@ -28,12 +28,12 @@ define dso_local ventus_kernel void @float_add(ptr addrspace(1) nocapture nounde
; VENTUS: .cfi_startproc
; VENTUS: # %bb.0:
; VENTUS-NEXT: lw t0, 4(a0)
; VENTUS-NEXT: flw t0, 0(t0)
; VENTUS-NEXT: lw t0, 0(t0)
; VENTUS-NEXT: lui t1, %hi(.LCPI1_0)
; VENTUS-NEXT: flw t1, %lo(.LCPI1_0)(t1)
; VENTUS-NEXT: lw t1, %lo(.LCPI1_0)(t1)
; VENTUS-NEXT: fadd.s t0, t0, t1
; VENTUS-NEXT: lw t1, 0(a0)
; VENTUS-NEXT: fsw t0, 0(t1)
; VENTUS-NEXT: sw t0, 0(t1)
; VENTUS-NEXT: ret
entry: