From 4354b039f30102cb9a1d738d45c92b17ad78e354 Mon Sep 17 00:00:00 2001 From: ziliangzl Date: Thu, 25 Apr 2024 10:44:57 +0800 Subject: [PATCH 1/2] [VENTUS][fix]Fix FLW/FSW instruction coding conflict Replace FLW/FSW instruction with PseudoFLW/PseudoFSW --- llvm/lib/Target/RISCV/VentusInstrInfoF.td | 56 +++++++++++------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/llvm/lib/Target/RISCV/VentusInstrInfoF.td b/llvm/lib/Target/RISCV/VentusInstrInfoF.td index fbb59ea30c2c..312f2c7b211b 100644 --- a/llvm/lib/Target/RISCV/VentusInstrInfoF.td +++ b/llvm/lib/Target/RISCV/VentusInstrInfoF.td @@ -340,29 +340,7 @@ class PseudoVFROUND // Instructions //===----------------------------------------------------------------------===// -// FIXME: Ventus doesn't have FLW/FSW,it is same opcode with LW/SW -// but for GPRF32. -let Predicates = [HasStdExtZfinx] in { -/// Loads -def FLW : RVInstI<0b010, OPC_LOAD, (outs GPRF32:$rd), - (ins GPRMem:$rs1, simm12:$imm12), - "flw", "$rd, ${imm12}(${rs1})">, - Sched<[WriteLDW, ReadMemBase]>; -def : Pat<(f32 (UniformLoadFrag - (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))), - (FLW GPR:$rs1, simm12:$imm12)>; - -/// Stores -def FSW : RVInstS<0b010, OPC_STORE, (outs), - (ins GPRF32:$rs2, GPRMem:$rs1, simm12:$imm12), - "fsw", "$rs2, ${imm12}(${rs1})">, - Sched<[WriteSTW, ReadStoreData, ReadMemBase]>; - -def : Pat<(UniformStoreFrag (f32 GPRF32:$rs2), - (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)), - (FSW GPRF32:$rs2, GPR:$rs1, simm12:$imm12)>; -} // Predicates = [HasStdExtZfinx] let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in { defm FMADD_S : FPFMA_rrr_frm_m; @@ -466,8 +444,12 @@ defm : FPUnaryOpDynFrmAlias_m; //===----------------------------------------------------------------------===// let Predicates = [HasStdExtZfinx] in { -// def : InstAlias<"flw $rd, (${rs1})", (FLW GPRF32:$rd, GPR:$rs1, 0), 0>; -// def : InstAlias<"fsw $rs2, (${rs1})", (FSW GPRF32:$rs2, GPR:$rs1, 0), 0>; + +def : InstAlias<"flw $rd, ${imm12}(${rs1})", + (LW GPR:$rd, GPR:$rs1, simm12:$imm12)>; + +def : InstAlias<"fsw $rs2, ${imm12}(${rs1})", + (SW GPR:$rs2, GPR:$rs1, simm12:$imm12)>; def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>; def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>; @@ -510,8 +492,26 @@ def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, ui def : MnemonicAlias<"fmv.s.x", "fmv.w.x">; def : MnemonicAlias<"fmv.x.s", "fmv.x.w">; -def PseudoFLW : PseudoFloatLoad<"flw", GPRF32>; -def PseudoFSW : PseudoStore<"fsw", GPRF32>; +def PseudoFLW : Pseudo<(outs GPRF32:$rd), (ins GPRMem:$rs1, simm12:$imm12), [], + "flw", "$rd, ${imm12}(${rs1})">, + PseudoInstExpansion<(LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)> { + let hasSideEffects = 0; + let mayLoad = 1; + let mayStore = 0; + let isCodeGenOnly = 0; + let isAsmParserOnly = 1; +} + +def PseudoFSW : Pseudo<(outs), (ins GPRF32:$rs2, GPRMem:$rs1, simm12:$imm12), + [], "fsw", "$rs2, ${imm12}(${rs1})">, + PseudoInstExpansion<(SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)> { + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 1; + let isCodeGenOnly = 0; + let isAsmParserOnly = 1; +} + let usesCustomInserter = 1 in { def PseudoQuietFLE_S : PseudoQuietFCMP; def PseudoQuietFLT_S : PseudoQuietFCMP; @@ -654,11 +654,11 @@ def PseudoFROUND_S : PseudoFROUND; // /// Loads -// defm : UniformLdPat; +defm : UniformLdPat; // /// Stores -// defm : UniformStPat; +defm : UniformStPat; } // Predicates = [HasStdExtZfinx] From 8be31506966141b1bc199c10dcd8ca78a0fe51a6 Mon Sep 17 00:00:00 2001 From: ziliangzl Date: Fri, 26 Apr 2024 10:59:35 +0800 Subject: [PATCH 2/2] [#112][fix]Remove flw/fsw InstAlias 1.Removed flw/fsw InstAlias for now,cause flw/fsw could not match correctly. 2.Modified kernel_arg testcase. --- llvm/lib/Target/RISCV/VentusInstrInfoF.td | 8 ++++---- llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/RISCV/VentusInstrInfoF.td b/llvm/lib/Target/RISCV/VentusInstrInfoF.td index 312f2c7b211b..99a1f5a2eea6 100644 --- a/llvm/lib/Target/RISCV/VentusInstrInfoF.td +++ b/llvm/lib/Target/RISCV/VentusInstrInfoF.td @@ -445,11 +445,11 @@ defm : FPUnaryOpDynFrmAlias_m; let Predicates = [HasStdExtZfinx] in { -def : InstAlias<"flw $rd, ${imm12}(${rs1})", - (LW GPR:$rd, GPR:$rs1, simm12:$imm12)>; +// def : InstAlias<"flw $rd, ${imm12}(${rs1})", +// (LW GPR:$rd, GPR:$rs1, simm12:$imm12)>; -def : InstAlias<"fsw $rs2, ${imm12}(${rs1})", - (SW GPR:$rs2, GPR:$rs1, simm12:$imm12)>; +// def : InstAlias<"fsw $rs2, ${imm12}(${rs1})", +// (SW GPR:$rs2, GPR:$rs1, simm12:$imm12)>; def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>; def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>; diff --git a/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll b/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll index 5b129766e1e0..c9b2461bb6a4 100644 --- a/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll +++ b/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll @@ -28,12 +28,12 @@ define dso_local ventus_kernel void @float_add(ptr addrspace(1) nocapture nounde ; VENTUS: .cfi_startproc ; VENTUS: # %bb.0: ; VENTUS-NEXT: lw t0, 4(a0) -; VENTUS-NEXT: flw t0, 0(t0) +; VENTUS-NEXT: lw t0, 0(t0) ; VENTUS-NEXT: lui t1, %hi(.LCPI1_0) -; VENTUS-NEXT: flw t1, %lo(.LCPI1_0)(t1) +; VENTUS-NEXT: lw t1, %lo(.LCPI1_0)(t1) ; VENTUS-NEXT: fadd.s t0, t0, t1 ; VENTUS-NEXT: lw t1, 0(a0) -; VENTUS-NEXT: fsw t0, 0(t1) +; VENTUS-NEXT: sw t0, 0(t1) ; VENTUS-NEXT: ret entry: