diff --git a/llvm/lib/Target/RISCV/VentusInstrInfoF.td b/llvm/lib/Target/RISCV/VentusInstrInfoF.td
index c12818efd141..e5d0ddc864be 100644
--- a/llvm/lib/Target/RISCV/VentusInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/VentusInstrInfoF.td
@@ -656,13 +656,14 @@ defm Select_FPR32 : SelectCC_GPR_rrirr<GPRF32>;
 def PseudoVFROUND_S : PseudoVFROUND<VGPR>;
 def PseudoFROUND_S : PseudoFROUND<GPRF32>;
 
-// /// Loads
+/// Loads
 
-defm : UniformLdPat<load, PseudoFLW, f32>;
+def : Pat<(f32 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
+          (COPY_TO_REGCLASS (LW GPR:$rs1, simm12:$imm12), GPRF32)>;
 
-// /// Stores
-
-defm : UniformStPat<store, PseudoFSW, GPRF32, f32>;
+/// Stores
+def : Pat<(store (f32 FPR32INX:$rs2), (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
+          (SW (COPY_TO_REGCLASS FPR32INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>;
 
 } // Predicates = [HasStdExtZfinx]
 
diff --git a/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll b/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll
index 26c93d52da2b..13b11d503dd7 100644
--- a/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll
+++ b/llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll
@@ -29,12 +29,12 @@ define dso_local ventus_kernel void @float_add(ptr addrspace(1) nocapture nounde
 ; VENTUS-LABEL: float_add:
 ; VENTUS:       # %bb.0: # %entry
 ; VENTUS-NEXT:    lw t0, 4(a0)
-; VENTUS-NEXT:    flw t0, 0(t0)
+; VENTUS-NEXT:    lw t0, 0(t0)
 ; VENTUS-NEXT:    lui t1, %hi(.LCPI1_0)
-; VENTUS-NEXT:    flw t1, %lo(.LCPI1_0)(t1)
+; VENTUS-NEXT:    lw t1, %lo(.LCPI1_0)(t1)
 ; VENTUS-NEXT:    fadd.s t0, t0, t1
 ; VENTUS-NEXT:    lw t1, 0(a0)
-; VENTUS-NEXT:    fsw t0, 0(t1)
+; VENTUS-NEXT:    sw t0, 0(t1)
 ; VENTUS-OBJ:    lw      t1, 0(t1)
 ; VENTUS-OBJ:    fadd.s  t0, t0, t1
 ; VENTUS-NEXT:    ret