forked from rcore-os/zCore
refactor(drivers): 修改 io
- 根据 wikipedia，pio 改名 pmio - 为 mmio 读写增加内存屏障 - 为 io 补充文档
This commit is contained in:
parent
fcc46ebfc5
commit
99f21ba488
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@ -1,12 +1,10 @@
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use core::mem::MaybeUninit;
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use super::Io;
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use core::ops::{BitAnd, BitOr, Not};
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use super::Io;
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// 主存映射 I/O。
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/// Memory-mapped I/O.
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#[repr(transparent)]
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pub struct Mmio<T> {
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value: MaybeUninit<T>,
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}
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pub struct Mmio<T>(T);
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impl<T> Mmio<T> {
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/// # Safety
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@ -25,9 +23,7 @@ impl<T> Mmio<T> {
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}
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pub fn add<'a>(&self, offset: usize) -> &'a mut Self {
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unsafe {
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Self::from_base(self.value.as_ptr() as usize + offset * core::mem::size_of::<T>())
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}
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unsafe { Self::from_base((&self.0 as *const T).add(offset) as _) }
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}
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}
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@ -38,10 +34,19 @@ where
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type Value = T;
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fn read(&self) -> T {
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unsafe { core::ptr::read_volatile(self.value.as_ptr()) }
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unsafe {
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let val = core::ptr::read_volatile(&self.0 as *const _);
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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core::arch::asm!("fence i,r");
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val
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}
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}
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fn write(&mut self, value: T) {
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unsafe { core::ptr::write_volatile(self.value.as_mut_ptr(), value) };
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unsafe {
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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core::arch::asm!("fence w,o");
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core::ptr::write_volatile(&mut self.0 as *mut _, value)
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};
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}
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}
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@ -1,57 +1,79 @@
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//! General MMIO and PIO device driver.
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// 封装对外设地址空间的访问，包括内存映射 IO 和端口映射 IO。
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//
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// 要了解这两种访问外设的方式，查看[维基百科](https://en.wikipedia.org/wiki/Memory-mapped_I/O)。
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//! Peripheral address space access, including memory-mapped IO and port-mapped IO.
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//!
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//! About these two methods of performing I/O, see [wikipedia](https://en.wikipedia.org/wiki/Memory-mapped_I/O).
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use core::ops::{BitAnd, BitOr, Not};
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mod mmio;
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#[cfg(target_arch = "x86_64")]
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mod pio;
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mod pmio;
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pub use mmio::Mmio;
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#[cfg(target_arch = "x86_64")]
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pub use pio::Pio;
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pub use pmio::Pmio;
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// 用于处理外设地址空间访问的接口。
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/// An interface for dealing with device address space access.
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pub trait Io {
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// 可访问的对象的类型。
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/// The type of object to access.
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type Value: Copy
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+ BitAnd<Output = Self::Value>
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+ BitOr<Output = Self::Value>
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+ Not<Output = Self::Value>;
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// 从外设读取值。
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/// Reads value from device.
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fn read(&self) -> Self::Value;
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// 向外设写入值。
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/// Writes `value` to device.
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fn write(&mut self, value: Self::Value);
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}
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// 外设地址空间的一个只读单元。
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/// A readonly unit in device address space.
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#[repr(transparent)]
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pub struct ReadOnly<I> {
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inner: I,
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}
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pub struct ReadOnly<I>(I);
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impl<I> ReadOnly<I> {
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pub const fn new(inner: I) -> ReadOnly<I> {
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ReadOnly { inner }
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// 构造外设地址空间的一个只读单元。
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/// Constructs a readonly unit in device address space.
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pub const fn new(inner: I) -> Self {
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Self(inner)
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}
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}
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impl<I: Io> ReadOnly<I> {
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// 从外设读取值。
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/// Reads value from device.
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#[inline(always)]
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pub fn read(&self) -> I::Value {
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self.inner.read()
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self.0.read()
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}
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}
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// 外设地址空间的一个只写单元。
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/// A write-only unit in device address space.
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#[repr(transparent)]
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pub struct WriteOnly<I> {
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inner: I,
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}
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pub struct WriteOnly<I>(I);
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impl<I> WriteOnly<I> {
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pub const fn new(inner: I) -> WriteOnly<I> {
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WriteOnly { inner }
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// 构造外设地址空间的一个只写单元。
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/// Constructs a write-only unit in device address space.
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pub const fn new(inner: I) -> Self {
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Self(inner)
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}
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}
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impl<I: Io> WriteOnly<I> {
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// 向外设写入值。
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/// Writes `value` to device.
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#[inline(always)]
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pub fn write(&mut self, value: I::Value) {
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self.inner.write(value)
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self.0.write(value);
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}
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}
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@ -1,30 +1,35 @@
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use core::arch::asm;
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use core::marker::PhantomData;
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// 端口映射 I/O。
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//! Port-mapped I/O.
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use super::Io;
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use core::{arch::asm, marker::PhantomData};
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/// Generic PIO
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// 端口映射 I/O。
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/// Port-mapped I/O.
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#[derive(Copy, Clone)]
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pub struct Pio<T> {
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pub struct Pmio<T> {
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port: u16,
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_phantom: PhantomData<T>,
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}
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impl<T> Pio<T> {
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/// Create a PIO from a given port
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impl<T> Pmio<T> {
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// 映射指定端口进行外设访问。
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/// Maps a given port to assess device.
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pub const fn new(port: u16) -> Self {
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Pio::<T> {
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Self {
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port,
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_phantom: PhantomData,
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}
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}
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}
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/// Read/Write for byte PIO
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impl Io for Pio<u8> {
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// 逐字节端口映射读写。
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/// Read/Write for byte PMIO.
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impl Io for Pmio<u8> {
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type Value = u8;
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/// Read
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// 读。
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/// Read.
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#[inline(always)]
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fn read(&self) -> u8 {
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let value: u8;
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@ -34,7 +39,8 @@ impl Io for Pio<u8> {
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value
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}
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/// Write
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// 写。
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/// Write.
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#[inline(always)]
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fn write(&mut self, value: u8) {
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unsafe {
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@ -43,11 +49,13 @@ impl Io for Pio<u8> {
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}
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}
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/// Read/Write for word PIO
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impl Io for Pio<u16> {
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// 逐字端口映射读写。
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/// Read/Write for word PMIO.
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impl Io for Pmio<u16> {
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type Value = u16;
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/// Read
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// 读。
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/// Read.
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#[inline(always)]
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fn read(&self) -> u16 {
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let value: u16;
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@ -57,7 +65,8 @@ impl Io for Pio<u16> {
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value
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}
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/// Write
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// 写。
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/// Write.
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#[inline(always)]
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fn write(&mut self, value: u16) {
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unsafe {
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@ -66,11 +75,13 @@ impl Io for Pio<u16> {
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}
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}
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/// Read/Write for doubleword PIO
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impl Io for Pio<u32> {
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// 逐双字端口映射读写。
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/// Read/Write for double-word PMIO.
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impl Io for Pmio<u32> {
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type Value = u32;
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/// Read
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// 读。
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/// Read.
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#[inline(always)]
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fn read(&self) -> u32 {
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let value: u32;
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@ -80,7 +91,8 @@ impl Io for Pio<u32> {
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value
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}
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/// Write
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// 写。
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/// Write.
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#[inline(always)]
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fn write(&mut self, value: u32) {
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unsafe {
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@ -38,8 +38,7 @@ impl PlicUnlocked {
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let hart_id = cpu_id() as usize;
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let mmio = self
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.enable_base
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.add(PLIC_ENABLE_HART_OFFSET * hart_id)
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.add(irq_num / 32);
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.add(PLIC_ENABLE_HART_OFFSET * hart_id + irq_num / 32);
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let mask = 1 << (irq_num % 32);
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if enable {
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@ -54,8 +53,7 @@ impl PlicUnlocked {
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let hart_id = cpu_id() as usize;
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let irq_num = self
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.context_base
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.add(PLIC_CONTEXT_CLAIM_HART_OFFSET * hart_id)
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.add(PLIC_CONTEXT_CLAIM)
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.add(PLIC_CONTEXT_CLAIM_HART_OFFSET * hart_id + PLIC_CONTEXT_CLAIM)
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.read() as usize;
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if irq_num == 0 {
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None
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@ -69,8 +67,7 @@ impl PlicUnlocked {
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debug_assert!(IRQ_RANGE.contains(&irq_num));
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let hart_id = cpu_id() as usize;
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self.context_base
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.add(PLIC_CONTEXT_CLAIM)
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.add(PLIC_CONTEXT_CLAIM_HART_OFFSET * hart_id)
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.add(PLIC_CONTEXT_CLAIM + PLIC_CONTEXT_CLAIM_HART_OFFSET * hart_id)
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.write(irq_num as _);
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}
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@ -84,8 +81,7 @@ impl PlicUnlocked {
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fn set_threshold(&mut self, threshold: u8) {
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let hart_id = cpu_id() as usize;
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self.context_base
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.add(PLIC_PRIORITY_HART_OFFSET * hart_id)
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.add(PLIC_CONTEXT_THRESHOLD)
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.add(PLIC_PRIORITY_HART_OFFSET * hart_id + PLIC_CONTEXT_THRESHOLD)
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.write(threshold as _);
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}
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@ -7,4 +7,4 @@ pub use buffered::BufferedUart;
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pub use uart_16550::Uart16550Mmio;
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#[cfg(target_arch = "x86_64")]
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pub use uart_16550::Uart16550Pio;
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pub use uart_16550::Uart16550Pmio;
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@ -201,21 +201,21 @@ impl Uart16550Mmio<u32> {
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}
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#[cfg(target_arch = "x86_64")]
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mod pio {
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mod pmio {
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use super::*;
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use crate::io::Pio;
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use crate::io::Pmio;
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/// PIO driver for UART 16550
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pub struct Uart16550Pio {
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inner: Mutex<Uart16550Inner<Pio<u8>>>,
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/// Pmio driver for UART 16550
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pub struct Uart16550Pmio {
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inner: Mutex<Uart16550Inner<Pmio<u8>>>,
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listener: EventListener,
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}
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impl_event_scheme!(Uart16550Pio);
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impl_event_scheme!(Uart16550Pmio);
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impl Scheme for Uart16550Pio {
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impl Scheme for Uart16550Pmio {
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fn name(&self) -> &str {
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"uart16550-pio"
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"uart16550-Pmio"
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}
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fn handle_irq(&self, _irq_num: usize) {
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@ -223,7 +223,7 @@ mod pio {
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}
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}
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impl UartScheme for Uart16550Pio {
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impl UartScheme for Uart16550Pmio {
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fn try_recv(&self) -> DeviceResult<Option<u8>> {
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self.inner.lock().try_recv()
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}
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@ -237,17 +237,17 @@ mod pio {
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}
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}
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impl Uart16550Pio {
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/// Construct a `Uart16550Pio` whose address starts at `base`.
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impl Uart16550Pmio {
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/// Construct a `Uart16550Pmio` whose address starts at `base`.
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pub fn new(base: u16) -> Self {
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let mut uart = Uart16550Inner::<Pio<u8>> {
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data: Pio::new(base),
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int_en: Pio::new(base + 1),
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fifo_ctrl: Pio::new(base + 2),
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line_ctrl: Pio::new(base + 3),
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modem_ctrl: Pio::new(base + 4),
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line_sts: ReadOnly::new(Pio::new(base + 5)),
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modem_sts: ReadOnly::new(Pio::new(base + 6)),
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let mut uart = Uart16550Inner::<Pmio<u8>> {
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data: Pmio::new(base),
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int_en: Pmio::new(base + 1),
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fifo_ctrl: Pmio::new(base + 2),
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line_ctrl: Pmio::new(base + 3),
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modem_ctrl: Pmio::new(base + 4),
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line_sts: ReadOnly::new(Pmio::new(base + 5)),
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modem_sts: ReadOnly::new(Pmio::new(base + 6)),
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};
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uart.init();
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Self {
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@ -259,4 +259,4 @@ mod pio {
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}
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#[cfg(target_arch = "x86_64")]
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pub use pio::Uart16550Pio;
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pub use pmio::Uart16550Pmio;
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@ -26,8 +26,8 @@ hal_fn_impl! {
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fn reset() -> ! {
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info!("shutdown...");
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loop {
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use zcore_drivers::io::{Io, Pio};
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Pio::<u16>::new(0x604).write(0x2000);
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use zcore_drivers::io::{Io, Pmio};
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Pmio::<u16>::new(0x604).write(0x2000);
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super::interrupt::wait_for_interrupt();
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}
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}
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@ -3,16 +3,16 @@ use alloc::{boxed::Box, sync::Arc};
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use zcore_drivers::bus::pci;
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use zcore_drivers::irq::x86::Apic;
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use zcore_drivers::scheme::IrqScheme;
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use zcore_drivers::uart::{BufferedUart, Uart16550Pio};
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use zcore_drivers::uart::{BufferedUart, Uart16550Pmio};
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use zcore_drivers::{Device, DeviceResult};
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use super::trap;
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use crate::drivers;
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pub(super) fn init_early() -> DeviceResult {
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let uart = Arc::new(Uart16550Pio::new(0x3F8));
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let uart = Arc::new(Uart16550Pmio::new(0x3F8));
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drivers::add_device(Device::Uart(BufferedUart::new(uart)));
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let uart = Arc::new(Uart16550Pio::new(0x2F8));
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let uart = Arc::new(Uart16550Pmio::new(0x2F8));
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drivers::add_device(Device::Uart(BufferedUart::new(uart)));
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Ok(())
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}
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|
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@ -1,6 +1,6 @@
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//! Functions only available on x86 platforms.
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pub use zcore_drivers::io::{Io, Pio};
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pub use zcore_drivers::io::{Io, Pmio};
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/// Get physical address of `acpi_rsdp` and `smbios` on x86_64.
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pub fn pc_firmware_tables() -> (u64, u64) {
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|
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@ -3,7 +3,7 @@ use super::nodes::{
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SharedLegacyIrqHandler,
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};
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use super::{
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config::PciConfig, constants::*, pci_init_args::PciIrqSwizzleLut, pio::pci_bdf_raw_addr,
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config::PciConfig, constants::*, pci_init_args::PciIrqSwizzleLut, pmio::pci_bdf_raw_addr,
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MappedEcamRegion, PciAddrSpace, PciEcamRegion,
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};
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use crate::dev::Interrupt;
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@ -447,9 +447,9 @@ impl PCIeAddressProvider for MmioPcieAddressProvider {
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/// Systems that have PIO mapped Config Spaces.
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#[derive(Default)]
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pub struct PioPcieAddressProvider;
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pub struct PmioPcieAddressProvider;
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impl PCIeAddressProvider for PioPcieAddressProvider {
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impl PCIeAddressProvider for PmioPcieAddressProvider {
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fn create_config(&self, addr: u64) -> Arc<PciConfig> {
|
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Arc::new(PciConfig {
|
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addr_space: PciAddrSpace::PIO,
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|
|
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|
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@ -1,4 +1,4 @@
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use super::pio::{pio_config_read_addr, pio_config_write_addr};
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||||
use super::pmio::{pmio_config_read_addr, pmio_config_write_addr};
|
||||
use super::PciAddrSpace;
|
||||
use numeric_enum_macro::numeric_enum;
|
||||
|
||||
|
|
@ -14,21 +14,21 @@ impl PciConfig {
|
|||
trace!("read8 @ {:#x?}", offset);
|
||||
match self.addr_space {
|
||||
PciAddrSpace::MMIO => unsafe { u8::from_le(*(offset as *const u8)) },
|
||||
PciAddrSpace::PIO => pio_config_read_addr(offset as u32, 8).unwrap() as u8,
|
||||
PciAddrSpace::PIO => pmio_config_read_addr(offset as u32, 8).unwrap() as u8,
|
||||
}
|
||||
}
|
||||
pub fn read16_offset(&self, addr: usize) -> u16 {
|
||||
trace!("read16 @ {:#x?}", addr);
|
||||
match self.addr_space {
|
||||
PciAddrSpace::MMIO => unsafe { u16::from_le(*(addr as *const u16)) },
|
||||
PciAddrSpace::PIO => pio_config_read_addr(addr as u32, 16).unwrap() as u16,
|
||||
PciAddrSpace::PIO => pmio_config_read_addr(addr as u32, 16).unwrap() as u16,
|
||||
}
|
||||
}
|
||||
pub fn read32_offset(&self, addr: usize) -> u32 {
|
||||
trace!("read32 @ {:#x?}", addr);
|
||||
match self.addr_space {
|
||||
PciAddrSpace::MMIO => unsafe { u32::from_le(*(addr as *const u32)) },
|
||||
PciAddrSpace::PIO => pio_config_read_addr(addr as u32, 32).unwrap(),
|
||||
PciAddrSpace::PIO => pmio_config_read_addr(addr as u32, 32).unwrap(),
|
||||
}
|
||||
}
|
||||
pub fn read8(&self, addr: PciReg8) -> u8 {
|
||||
|
|
@ -56,7 +56,7 @@ impl PciConfig {
|
|||
pub fn write8_offset(&self, addr: usize, val: u8) {
|
||||
match self.addr_space {
|
||||
PciAddrSpace::MMIO => unsafe { *(addr as *mut u8) = val },
|
||||
PciAddrSpace::PIO => pio_config_write_addr(addr as u32, val as u32, 8).unwrap(),
|
||||
PciAddrSpace::PIO => pmio_config_write_addr(addr as u32, val as u32, 8).unwrap(),
|
||||
}
|
||||
}
|
||||
pub fn write16_offset(&self, addr: usize, val: u16) {
|
||||
|
|
@ -67,13 +67,13 @@ impl PciConfig {
|
|||
);
|
||||
match self.addr_space {
|
||||
PciAddrSpace::MMIO => unsafe { *(addr as *mut u16) = val },
|
||||
PciAddrSpace::PIO => pio_config_write_addr(addr as u32, val as u32, 16).unwrap(),
|
||||
PciAddrSpace::PIO => pmio_config_write_addr(addr as u32, val as u32, 16).unwrap(),
|
||||
}
|
||||
}
|
||||
pub fn write32_offset(&self, addr: usize, val: u32) {
|
||||
match self.addr_space {
|
||||
PciAddrSpace::MMIO => unsafe { *(addr as *mut u32) = val },
|
||||
PciAddrSpace::PIO => pio_config_write_addr(addr as u32, val as u32, 32).unwrap(),
|
||||
PciAddrSpace::PIO => pmio_config_write_addr(addr as u32, val as u32, 32).unwrap(),
|
||||
}
|
||||
}
|
||||
pub fn write8(&self, addr: PciReg8, val: u8) {
|
||||
|
|
|
|||
|
|
@ -5,14 +5,14 @@ mod caps;
|
|||
mod config;
|
||||
mod nodes;
|
||||
pub mod pci_init_args;
|
||||
mod pio;
|
||||
mod pmio;
|
||||
|
||||
pub use self::bus::{
|
||||
MmioPcieAddressProvider, PCIeBusDriver, PcieDeviceInfo, PcieDeviceKObject,
|
||||
PioPcieAddressProvider,
|
||||
PmioPcieAddressProvider,
|
||||
};
|
||||
pub use self::nodes::{IPciNode, PcieIrqMode};
|
||||
pub use self::pio::{pio_config_read, pio_config_write};
|
||||
pub use self::pmio::{pio_config_read, pio_config_write};
|
||||
|
||||
/// Type of PCI address space.
|
||||
#[derive(PartialEq, Debug)]
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ pub fn pci_bdf_raw_addr(bus: u8, dev: u8, func: u8, offset: u8) -> u32 {
|
|||
|
||||
cfg_if::cfg_if! {
|
||||
if #[cfg(all(target_arch = "x86_64", target_os = "none"))] {
|
||||
use kernel_hal::x86_64::{Io, Pio};
|
||||
use kernel_hal::x86_64::{Io, Pmio};
|
||||
use spin::Mutex;
|
||||
|
||||
static PIO_LOCK: Mutex<()> = Mutex::new(());
|
||||
|
|
@ -20,9 +20,9 @@ if #[cfg(all(target_arch = "x86_64", target_os = "none"))] {
|
|||
const PCI_CONFIG_DATA: u16 = 0xcfc;
|
||||
const PCI_CONFIG_ENABLE: u32 = 1 << 31;
|
||||
|
||||
pub fn pio_config_read_addr(addr: u32, width: usize) -> ZxResult<u32> {
|
||||
let mut port_cfg = Pio::<u32>::new(PCI_CONFIG_ADDR);
|
||||
let port_data = Pio::<u32>::new(PCI_CONFIG_DATA);
|
||||
pub fn pmio_config_read_addr(addr: u32, width: usize) -> ZxResult<u32> {
|
||||
let mut port_cfg = Pmio::<u32>::new(PCI_CONFIG_ADDR);
|
||||
let port_data = Pmio::<u32>::new(PCI_CONFIG_DATA);
|
||||
|
||||
let _lock = PIO_LOCK.lock();
|
||||
let shift = ((addr & 0x3) << 3) as usize;
|
||||
|
|
@ -33,9 +33,9 @@ if #[cfg(all(target_arch = "x86_64", target_os = "none"))] {
|
|||
let tmp_val = u32::from_le(port_data.read());
|
||||
Ok((tmp_val >> shift) & (((1u64 << width) - 1) as u32))
|
||||
}
|
||||
pub fn pio_config_write_addr(addr: u32, val: u32, width: usize) -> ZxResult {
|
||||
let mut port_cfg = Pio::<u32>::new(PCI_CONFIG_ADDR);
|
||||
let mut port_data = Pio::<u32>::new(PCI_CONFIG_DATA);
|
||||
pub fn pmio_config_write_addr(addr: u32, val: u32, width: usize) -> ZxResult {
|
||||
let mut port_cfg = Pmio::<u32>::new(PCI_CONFIG_ADDR);
|
||||
let mut port_data = Pmio::<u32>::new(PCI_CONFIG_DATA);
|
||||
|
||||
let _lock = PIO_LOCK.lock();
|
||||
let shift = ((addr & 0x3) << 3) as usize;
|
||||
|
|
@ -54,17 +54,17 @@ if #[cfg(all(target_arch = "x86_64", target_os = "none"))] {
|
|||
Ok(())
|
||||
}
|
||||
} else {
|
||||
pub fn pio_config_read_addr(_addr: u32, _width: usize) -> ZxResult<u32> {
|
||||
pub fn pmio_config_read_addr(_addr: u32, _width: usize) -> ZxResult<u32> {
|
||||
Err(ZxError::NOT_SUPPORTED)
|
||||
}
|
||||
pub fn pio_config_write_addr(_addr: u32, _val: u32, _width: usize) -> ZxResult {
|
||||
pub fn pmio_config_write_addr(_addr: u32, _val: u32, _width: usize) -> ZxResult {
|
||||
Err(ZxError::NOT_SUPPORTED)
|
||||
}
|
||||
}
|
||||
} // cfg_if!
|
||||
|
||||
pub fn pio_config_read(bus: u8, dev: u8, func: u8, offset: u8, width: usize) -> ZxResult<u32> {
|
||||
pio_config_read_addr(pci_bdf_raw_addr(bus, dev, func, offset), width)
|
||||
pmio_config_read_addr(pci_bdf_raw_addr(bus, dev, func, offset), width)
|
||||
}
|
||||
|
||||
pub fn pio_config_write(
|
||||
|
|
@ -75,5 +75,5 @@ pub fn pio_config_write(
|
|||
val: u32,
|
||||
width: usize,
|
||||
) -> ZxResult {
|
||||
pio_config_write_addr(pci_bdf_raw_addr(bus, dev, func, offset), val, width)
|
||||
pmio_config_write_addr(pci_bdf_raw_addr(bus, dev, func, offset), val, width)
|
||||
}
|
||||
|
|
@ -6,7 +6,7 @@ use zircon_object::{
|
|||
constants::*,
|
||||
pci_init_args::{PciInitArgsAddrWindows, PciInitArgsHeader, PCI_INIT_ARG_MAX_SIZE},
|
||||
MmioPcieAddressProvider, PCIeBusDriver, PciAddrSpace, PciEcamRegion, PcieDeviceInfo,
|
||||
PcieDeviceKObject, PcieIrqMode, PioPcieAddressProvider,
|
||||
PcieDeviceKObject, PcieIrqMode, PmioPcieAddressProvider,
|
||||
},
|
||||
dev::{Resource, ResourceKind},
|
||||
vm::{pages, VmObject},
|
||||
|
|
@ -143,7 +143,7 @@ impl Syscall<'_> {
|
|||
})?;
|
||||
PCIeBusDriver::set_address_translation_provider(addr_provider)?;
|
||||
} else if addr_win.cfg_space_type == PCI_CFG_SPACE_TYPE_PIO {
|
||||
let addr_provider = Arc::new(PioPcieAddressProvider::default());
|
||||
let addr_provider = Arc::new(PmioPcieAddressProvider::default());
|
||||
PCIeBusDriver::set_address_translation_provider(addr_provider)?;
|
||||
} else {
|
||||
return Err(ZxError::INVALID_ARGS);
|
||||
|
|
|
|||
Loading…
Reference in New Issue