Use multiclock mode in formal verification

2024-02-19 01:42:59 +01:00 · 2024-02-19 01:42:59 +01:00 · 4a441dd47a
parent 3b84555158
commit 4a441dd47a
1 changed files with 1 additions and 1 deletions
--- a/hw/spinal/projectname/MyTopLevelFormal.scala
+++ b/hw/spinal/projectname/MyTopLevelFormal.scala
@ -6,7 +6,7 @@ import spinal.core.formal._
 // You need SymbiYosys to be installed.
 // See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
 object MyTopLevelFormal extends App {
-  FormalConfig
+  SpinalFormalConfig( _hasAsync = true )
    .withBMC(10)
    .doVerify(new Component {
      val dut = FormalDut(MyTopLevel())