forked from xuos/xiuos
13 changed files with 1086 additions and 1554 deletions
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/**
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******************************************************************************* |
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* @file i2c/i2c_master_polling/source/main.c |
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* @brief Main program of I2C master polling for the Device Driver Library. |
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@verbatim |
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Change Logs: |
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Date Author Notes |
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2020-06-12 Hexiao First version |
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2020-08-31 Hexiao Modify I2C init flow |
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2020-09-04 Hexiao Modify compile warning |
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2021-01-21 Hexiao Replace PWC_FCG1_IIC1 with PWC_FCG1_I2C1 |
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@endverbatim |
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******************************************************************************* |
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. |
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* |
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* This software component is licensed by HDSC under BSD 3-Clause license |
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* (the "License"); You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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******************************************************************************* |
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*/ |
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/*******************************************************************************
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* Include files |
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******************************************************************************/ |
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#include <nuttx/config.h> |
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#include <sys/types.h> |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <stdint.h> |
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#include <stdbool.h> |
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#include <assert.h> |
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#include <errno.h> |
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#include <debug.h> |
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#include <nuttx/arch.h> |
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#include <nuttx/irq.h> |
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#include <nuttx/clock.h> |
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#include <nuttx/semaphore.h> |
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#include <nuttx/i2c/i2c_master.h> |
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#include "hc32_ddl.h" |
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#include "hc32_gpio.h" |
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#include "hc32_uart.h" |
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/**
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* @addtogroup HC32F4A0_DDL_Examples |
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* @{ |
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*/ |
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/**
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* @addtogroup I2C_Master_Polling |
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* @{ |
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*/ |
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/*******************************************************************************
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* Local type definitions ('typedef') |
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******************************************************************************/ |
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define') |
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******************************************************************************/ |
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/* Define slave device address for example */ |
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#define DEVICE_ADDRESS (0x77U) //bmp180
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/* Define port and pin for SDA and SCL */ |
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#define I2C_SCL_PORT (GPIO_PORT_D) |
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#define I2C_SCL_PIN (GPIO_PIN_03) |
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#define I2C_SDA_PORT (GPIO_PORT_F) |
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#define I2C_SDA_PIN (GPIO_PIN_10) |
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#define I2C_RET_OK (0U) |
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#define I2C_RET_ERROR (1U) |
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#define GENERATE_START (0x00U) |
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#define GENERATE_RESTART (0x01U) |
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#define ADDRESS_W (0x00U) |
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#define ADDRESS_R (0x01U) |
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/* Define Write and read data length for the example */ |
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#define TEST_DATA_LEN (1U) |
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/* Define i2c baudrate */ |
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#define I2C_BAUDRATE (400000UL) |
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//#define LED_GREEN_PORT (GPIO_PORT_I)
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//#define LED_GREEN_PIN (GPIO_PIN_03)
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#define I2C_MASTER 1 |
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#define I2C_SLAVE 2 |
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern') |
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******************************************************************************/ |
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/* I2C Device hardware configuration */ |
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struct hc32_i2c_config_s |
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{ |
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M4_I2C_TypeDef *base; /* I2C base address */ |
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gpio_pinset_t scl_pin; /* GPIO configuration for SCL as SCL */ |
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gpio_pinset_t sda_pin; /* GPIO configuration for SDA as SDA */ |
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uint8_t mode; /* Master or Slave mode */ |
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#ifndef CONFIG_I2C_POLLED |
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uint32_t irq; /* Event IRQ */ |
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#endif |
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}; |
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/* I2C Device Private Data */ |
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struct hc32_i2c_priv_s |
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{ |
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/* Standard I2C operations */ |
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const struct i2c_ops_s *ops; |
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/* Port configuration */ |
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const struct hc32_i2c_config_s *config; |
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int refs; /* Reference count */ |
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sem_t sem_excl; /* Mutual exclusion semaphore */ |
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#ifndef CONFIG_I2C_POLLED |
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sem_t sem_isr; /* Interrupt wait semaphore */ |
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#endif |
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volatile uint8_t intstate; /* Interrupt handshake (see enum hc32_intstate_e) */ |
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uint8_t msgc; /* Message count */ |
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struct i2c_msg_s *msgv; /* Message list */ |
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uint8_t *ptr; /* Current message buffer */ |
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uint32_t frequency; /* Current I2C frequency */ |
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int dcnt; /* Current message length */ |
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uint16_t flags; /* Current message flags */ |
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uint32_t status; /* End of transfer SR2|SR1 status */ |
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}; |
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static int hc32_i2c_init(FAR struct hc32_i2c_priv_s *priv); |
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static int hc32_i2c_deinit(FAR struct hc32_i2c_priv_s *priv); |
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static int hc32_i2c_transfer(FAR struct i2c_master_s *dev, |
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FAR struct i2c_msg_s *msgs, int count); |
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#ifdef CONFIG_I2C_RESET |
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static int hc32_i2c_reset(FAR struct i2c_master_s *dev); |
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#endif |
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/* I2C interface */ |
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static const struct i2c_ops_s hc32_i2c_ops = |
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{ |
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.transfer = hc32_i2c_transfer |
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#ifdef CONFIG_I2C_RESET |
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, .reset = hc32_i2c_reset |
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#endif |
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}; |
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/* I2C device structures */ |
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#ifdef CONFIG_HC32_I2C1 |
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static const struct hc32_i2c_config_s hc32_i2c1_config = |
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{ |
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.base = M4_I2C1, |
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.scl_pin = GPIO_PINSET(I2C_SCL_PORT, I2C_SCL_PIN), |
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.sda_pin = GPIO_PINSET(I2C_SDA_PORT, I2C_SDA_PIN), |
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#ifndef CONFIG_I2C_SLAVE |
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.mode = I2C_MASTER, |
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#else |
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.mode = I2C_SLAVE, |
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#endif |
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#ifndef CONFIG_I2C_POLLED |
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.irq = EVT_I2C1_RXI, |
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#endif |
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}; |
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static struct hc32_i2c_priv_s hc32_i2c1_priv = |
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{ |
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.ops = &hc32_i2c_ops, |
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.config = &hc32_i2c1_config, |
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.refs = 0, |
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.intstate = INTSTATE_IDLE, |
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.msgc = 0, |
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.msgv = NULL, |
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.ptr = NULL, |
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.dcnt = 0, |
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.flags = 0, |
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.status = 0 |
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}; |
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#endif |
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#ifdef CONFIG_HC32_I2C2 |
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static const struct hc32_i2c_config_s hc32_i2c2_config = |
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{ |
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.base = M4_I2C2, |
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.scl_pin = GPIO_PINSET(I2C_SCL_PORT, I2C_SCL_PIN), |
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.sda_pin = GPIO_PINSET(I2C_SDA_PORT, I2C_SDA_PIN), |
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#ifndef CONFIG_I2C_SLAVE |
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.mode = I2C_MASTER, |
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#else |
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.mode = I2C_SLAVE, |
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#endif |
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#ifndef CONFIG_I2C_POLLED |
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.irq = EVT_I2C2_RXI, |
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#endif |
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}; |
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static struct hc32_i2c_priv_s hc32_i2c2_priv = |
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{ |
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.ops = &hc32_i2c_ops, |
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.config = &hc32_i2c2_config, |
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.refs = 0, |
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.intstate = INTSTATE_IDLE, |
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.msgc = 0, |
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.msgv = NULL, |
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.ptr = NULL, |
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.dcnt = 0, |
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.flags = 0, |
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.status = 0 |
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}; |
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#endif |
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#ifdef CONFIG_HC32_I2C3 |
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static const struct hc32_i2c_config_s hc32_i2c3_config = |
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{ |
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.base = M4_I2C3, |
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.scl_pin = GPIO_PINSET(I2C_SCL_PORT, I2C_SCL_PIN), |
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.sda_pin = GPIO_PINSET(I2C_SDA_PORT, I2C_SDA_PIN), |
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#ifndef CONFIG_I2C_SLAVE |
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.mode = I2C_MASTER, |
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#else |
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.mode = I2C_SLAVE, |
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#endif |
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#ifndef CONFIG_I2C_POLLED |
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.irq = EVT_I2C3_RXI, |
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#endif |
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}; |
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static struct hc32_i2c_priv_s hc32_i2c3_priv = |
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{ |
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.ops = &hc32_i2c_ops, |
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.config = &hc32_i2c3_config, |
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.refs = 0, |
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.intstate = INTSTATE_IDLE, |
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.msgc = 0, |
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.msgv = NULL, |
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.ptr = NULL, |
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.dcnt = 0, |
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.flags = 0, |
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.status = 0 |
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}; |
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#endif |
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/*******************************************************************************
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* Local function prototypes ('static') |
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******************************************************************************/ |
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/*******************************************************************************
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* Local variable definitions ('static') |
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******************************************************************************/ |
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#define I2C_TIMEOUT (0x24000U) |
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static') |
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******************************************************************************/ |
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/**
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* @brief MCU Peripheral registers write unprotected. |
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* @param None |
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* @retval None |
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* @note Comment/uncomment each API depending on APP requires. |
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*/ |
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static void Peripheral_WE(void) |
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{ |
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/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ |
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GPIO_Unlock(); |
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/* Unlock PWC register: FCG0 */ |
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PWC_FCG0_Unlock(); |
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/* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */ |
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PWC_Unlock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1 | PWC_UNLOCK_CODE_2); |
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/* Unlock SRAM register: WTCR */ |
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SRAM_WTCR_Unlock(); |
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/* Unlock SRAM register: CKCR */ |
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SRAM_CKCR_Unlock(); |
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/* Unlock all EFM registers */ |
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EFM_Unlock(); |
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/* Unlock EFM register: FWMC */ |
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//EFM_FWMC_Unlock();
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/* Unlock EFM OTP write protect registers */ |
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//EFM_OTP_WP_Unlock();
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/* Unlock all MPU registers */ |
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// MPU_Unlock();
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} |
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/**
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* @brief MCU Peripheral registers write protected. |
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* @param None |
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* @retval None |
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* @note Comment/uncomment each API depending on APP requires. |
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*/ |
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static __attribute__((unused)) void Peripheral_WP(void) |
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{ |
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/* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ |
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GPIO_Lock(); |
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/* Lock PWC register: FCG0 */ |
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PWC_FCG0_Lock(); |
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/* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */ |
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PWC_Lock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1 | PWC_UNLOCK_CODE_2); |
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/* Lock SRAM register: WTCR */ |
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SRAM_WTCR_Lock(); |
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/* Lock SRAM register: CKCR */ |
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SRAM_CKCR_Lock(); |
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/* Lock EFM OTP write protect registers */ |
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//EFM_OTP_WP_Lock();
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/* Lock EFM register: FWMC */ |
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//EFM_FWMC_Lock();
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/* Lock all EFM registers */ |
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EFM_Lock(); |
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/* Lock all MPU registers */ |
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// MPU_Lock();
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} |
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//static void Master_LedInit(void)
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//{
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// stc_gpio_init_t stcGpioInit;
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//
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// /* RGB LED initialize */
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// (void)GPIO_StructInit(&stcGpioInit);
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// (void)GPIO_Init(LED_GREEN_PORT, LED_GREEN_PIN, &stcGpioInit);
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//
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// /* "Turn off" LED before set to output */
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// GPIO_ResetPins(LED_GREEN_PORT, LED_GREEN_PIN);
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//
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// /* Output enable */
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// GPIO_OE(LED_GREEN_PORT, LED_GREEN_PIN, Enable);
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//}
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//static void Master_LedOn(void)
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//{
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// GPIO_SetPins(LED_GREEN_PORT, LED_GREEN_PIN);
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//}
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/**
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* @brief Send start or restart condition |
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* @param [in] u8Start Indicate the start mode, start or restart |
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* @retval Process result |
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* - I2C_RET_ERROR Send start or restart failed |
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* - I2C_RET_OK Send start or restart success |
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*/ |
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static en_result_t Master_StartOrRestart(uint8_t u8Start) |
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{ |
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en_result_t enRet; |
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/* generate start or restart signal */ |
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if(GENERATE_START == u8Start) |
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{ |
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enRet = I2C_Start(M4_I2C1,I2C_TIMEOUT); |
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} |
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else |
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{ |
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/* Clear start status flag */ |
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enRet = I2C_Restart(M4_I2C1,I2C_TIMEOUT); |
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} |
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return enRet; |
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} |
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/**
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* @brief Send slave address |
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* @param [in] u8Adr The slave address |
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* @param [in] u8Dir The transfer direction @ref I2C_Transfer_Direction |
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* @retval Process result |
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* - I2C_RET_ERROR Send failed |
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* - I2C_RET_OK Send success |
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*/ |
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static en_result_t Master_SendAdr(uint8_t u8Adr, uint8_t u8Dir) |
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{ |
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return I2C_TransAddr(M4_I2C1,u8Adr,u8Dir,I2C_TIMEOUT); |
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} |
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/**
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* @brief Send data to slave |
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* @param [in] pTxData Pointer to the data buffer |
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* @param [in] u32Size Data size |
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* @retval Process result |
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* - I2C_RET_ERROR Send failed |
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* - I2C_RET_OK Send success |
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*/ |
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static en_result_t Master_WriteData(uint8_t const pTxData[], uint32_t u32Size) |
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{ |
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return I2C_TransData(M4_I2C1, pTxData, u32Size,I2C_TIMEOUT); |
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} |
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/**
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* @brief Write address and receive data from slave |
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* @param [in] pRxData Pointer to the data buffer |
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* @param [in] u32Size Data size |
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* @retval Process result |
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* - I2C_RET_ERROR Process failed |
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* - I2C_RET_OK Process success |
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*/ |
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static en_result_t Master_ReceiveAndStop(uint8_t pRxData[], uint32_t u32Size) |
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{ |
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return I2C_MasterReceiveAndStop(M4_I2C1,pRxData, u32Size,I2C_TIMEOUT); |
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} |
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/**
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* @brief General stop condition to slave |
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* @param None |
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* @retval Process result |
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* - I2C_RET_ERROR Process failed |
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* - I2C_RET_OK Process success |
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*/ |
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static en_result_t Master_Stop(void) |
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{ |
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return I2C_Stop(M4_I2C1,I2C_TIMEOUT); |
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} |
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/**
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* @brief Initialize the I2C peripheral for master |
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* @param None |
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* @retval Process result |
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* - I2C_RET_ERROR Process failed |
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* - I2C_RET_OK Process success |
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*/ |
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static en_result_t Master_Initialize(void) |
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{ |
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stc_i2c_init_t stcI2cInit; |
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float32_t fErr; |
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I2C_DeInit(M4_I2C1); |
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(void)I2C_StructInit(&stcI2cInit); |
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stcI2cInit.u32Baudrate = I2C_BAUDRATE; |
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stcI2cInit.u32SclTime = 5U; |
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stcI2cInit.u32ClkDiv = I2C_CLK_DIV4; |
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en_result_t enRet = I2C_Init(M4_I2C1, &stcI2cInit, &fErr); |
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I2C_BusWaitCmd(M4_I2C1, Enable); |
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if(enRet == Ok) |
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{ |
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I2C_Cmd(M4_I2C1, Enable); |
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} |
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return enRet; |
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} |
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/**
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* @brief Judge the result. LED0 toggle when result is error status. |
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* @param [in] enRet Result to be judged |
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* @retval None |
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*/ |
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static void JudgeResult(en_result_t enRet) |
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{ |
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if(Ok != enRet) |
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{ |
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for(;;) |
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{ |
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DDL_DelayMS(500U); |
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} |
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} |
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} |
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static int hc32_i2c_init(FAR struct hc32_i2c_priv_s *priv) |
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{ |
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return OK; |
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} |
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static int hc32_i2c_deinit(FAR struct hc32_i2c_priv_s *priv) |
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{ |
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return OK; |
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} |
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static inline void hc32_i2c_sem_init(FAR struct hc32_i2c_priv_s *priv) |
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{ |
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nxsem_init(&priv->sem_excl, 0, 1); |
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#ifndef CONFIG_I2C_POLLED |
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/* This semaphore is used for signaling and, hence, should not have
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* priority inheritance enabled. |
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*/ |
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nxsem_init(&priv->sem_isr, 0, 0); |
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nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); |
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#endif |
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} |
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static inline void hc32_i2c_sem_destroy(FAR struct hc32_i2c_priv_s *priv) |
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{ |
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nxsem_destroy(&priv->sem_excl); |
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#ifndef CONFIG_I2C_POLLED |
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nxsem_destroy(&priv->sem_isr); |
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#endif |
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} |
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/****************************************************************************
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* Name: hc32_i2c_sem_post |
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* |
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* Description: |
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* Release the mutual exclusion semaphore |
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* |
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****************************************************************************/ |
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static inline void hc32_i2c_sem_post(struct hc32_i2c_priv_s *priv) |
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{ |
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nxsem_post(&priv->sem_excl); |
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} |
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#if 0 |
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static int hc32_i2c_transfer1(FAR struct i2c_master_s *dev, |
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FAR struct i2c_msg_s *msgs, int count) |
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{ |
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FAR struct hc32_i2c_priv_s *priv = (struct hc32_i2c_priv_s *)dev; |
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uint32_t status = 0; |
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#ifdef I2C1_FSMC_CONFLICT |
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uint32_t ahbenr; |
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#endif |
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int ret; |
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DEBUGASSERT(count); |
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/* Ensure that address or flags don't change meanwhile */ |
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ret = nxsem_wait(&priv->sem_excl); |
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if (ret < 0) |
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{ |
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return ret; |
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} |
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//
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//
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|
|||
/* Ensure that any ISR happening after we finish can't overwrite any user
|
|||
* data |
|||
*/ |
|||
|
|||
priv->dcnt = 0; |
|||
priv->ptr = NULL; |
|||
|
|||
hc32_i2c_sem_post(priv); |
|||
return ret; |
|||
} |
|||
#endif |
|||
|
|||
static int hc32_i2c_transfer(FAR struct i2c_master_s *dev, |
|||
FAR struct i2c_msg_s *msgs, int count) |
|||
{ |
|||
en_result_t ret; |
|||
FAR struct hc32_i2c_priv_s *priv = (struct hc32_i2c_priv_s *)dev; |
|||
|
|||
/* Initialize I2C peripheral and enable function*/ |
|||
ret = Master_Initialize(); |
|||
JudgeResult(ret); |
|||
|
|||
/* I2C master data write*/ |
|||
ret = Master_StartOrRestart(GENERATE_START); |
|||
JudgeResult(ret); |
|||
ret = Master_SendAdr(msgs->addr, I2C_DIR_TX); |
|||
JudgeResult(ret); |
|||
ret = Master_WriteData(msgs->buffer, msgs->length); |
|||
JudgeResult(ret); |
|||
ret = Master_Stop(); |
|||
JudgeResult(ret); |
|||
|
|||
/* 5mS delay for device*/ |
|||
DDL_DelayMS(5U); |
|||
|
|||
/* I2C master data read*/ |
|||
ret = Master_StartOrRestart(GENERATE_START); |
|||
if(1UL == msgs->length) |
|||
{ |
|||
I2C_AckConfig(priv->config->base, I2C_NACK); |
|||
} |
|||
JudgeResult(ret); |
|||
ret = Master_SendAdr(msgs->addr, I2C_DIR_RX); |
|||
JudgeResult(ret); |
|||
ret = Master_ReceiveAndStop(msgs->buffer, msgs->length); |
|||
JudgeResult(ret); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
int hc32_i2c_config(void) |
|||
{ |
|||
/* Initialize I2C port*/ |
|||
stc_gpio_init_t stcGpioInit; |
|||
|
|||
Peripheral_WE(); |
|||
|
|||
(void)GPIO_StructInit(&stcGpioInit); |
|||
(void)GPIO_Init(I2C_SCL_PORT, I2C_SCL_PIN, &stcGpioInit); |
|||
(void)GPIO_Init(I2C_SDA_PORT, I2C_SDA_PIN, &stcGpioInit); |
|||
GPIO_SetFunc(I2C_SCL_PORT, I2C_SCL_PIN, GPIO_FUNC_49_I2C1_SCL, PIN_SUBFUNC_DISABLE); |
|||
GPIO_SetFunc(I2C_SDA_PORT, I2C_SDA_PIN, GPIO_FUNC_48_I2C1_SDA, PIN_SUBFUNC_DISABLE); |
|||
|
|||
/* Enable peripheral clock */ |
|||
PWC_Fcg1PeriphClockCmd(PWC_FCG1_I2C1, Enable); |
|||
return OK; |
|||
} |
|||
|
|||
|
|||
/**
|
|||
* @brief BSP clock initialize. |
|||
* Set board system clock to PLLH@240MHz |
|||
* Flash: 5 wait |
|||
* SRAM_HS: 1 wait |
|||
* SRAM1_2_3_4_B: 2 wait |
|||
* PCLK0: 240MHz |
|||
* PCLK1: 120MHz |
|||
* PCLK2: 60MHz |
|||
* PCLK3: 60MHz |
|||
* PCLK4: 120MHz |
|||
* EXCLK: 120MHz |
|||
* HCLK: 240MHz |
|||
* @param None |
|||
* @retval None |
|||
*/ |
|||
void BSP_CLK_Init(void) |
|||
{ |
|||
stc_clk_xtal_init_t stcXtalInit; |
|||
stc_clk_pllh_init_t stcPLLHInit; |
|||
|
|||
/* PCLK0, HCLK Max 240MHz */ |
|||
/* PCLK1, PCLK4 Max 120MHz */ |
|||
/* PCLK2, PCLK3 Max 60MHz */ |
|||
/* EX BUS Max 120MHz */ |
|||
CLK_ClkDiv(CLK_CATE_ALL, \ |
|||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ |
|||
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ |
|||
CLK_HCLK_DIV1)); |
|||
|
|||
CLK_XtalStructInit(&stcXtalInit); |
|||
/* Config Xtal and enable Xtal */ |
|||
stcXtalInit.u8XtalMode = CLK_XTALMODE_OSC; |
|||
stcXtalInit.u8XtalDrv = CLK_XTALDRV_LOW; |
|||
stcXtalInit.u8XtalState = CLK_XTAL_ON; |
|||
stcXtalInit.u8XtalStb = CLK_XTALSTB_2MS; |
|||
CLK_XtalInit(&stcXtalInit); |
|||
|
|||
(void)CLK_PLLHStructInit(&stcPLLHInit); |
|||
/* VCO = (8/1)*120 = 960MHz*/ |
|||
stcPLLHInit.u8PLLState = CLK_PLLH_ON; |
|||
stcPLLHInit.PLLCFGR = 0UL; |
|||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; |
|||
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; |
|||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; |
|||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; |
|||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; |
|||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL; |
|||
(void)CLK_PLLHInit(&stcPLLHInit); |
|||
|
|||
/* Highspeed SRAM set to 1 Read/Write wait cycle */ |
|||
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1); |
|||
|
|||
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */ |
|||
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2); |
|||
|
|||
/* 0-wait @ 40MHz */ |
|||
EFM_SetWaitCycle(EFM_WAIT_CYCLE_5); |
|||
|
|||
/* 4 cycles for 200 ~ 250MHz */ |
|||
GPIO_SetReadWaitCycle(GPIO_READ_WAIT_4); |
|||
|
|||
CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
* @brief Main function of i2c_master_polling project |
|||
* @param None |
|||
* @retval int32_t return value, if needed |
|||
*/ |
|||
int hc32_i2c_test(void) |
|||
{ |
|||
en_result_t enRet; |
|||
uint8_t u8TxBuf[TEST_DATA_LEN] = {0xD0}; |
|||
uint8_t u8RxBuf[TEST_DATA_LEN] = {0U}; |
|||
|
|||
hc32_i2c_config(); |
|||
|
|||
hc32_print("%s: %d start ...\n", __func__, __LINE__); |
|||
|
|||
/* Initialize I2C peripheral and enable function*/ |
|||
enRet = Master_Initialize(); |
|||
JudgeResult(enRet); |
|||
|
|||
hc32_print("%s: %d ret %d\n", __func__, __LINE__, enRet); |
|||
|
|||
/* I2C master data write*/ |
|||
enRet = Master_StartOrRestart(GENERATE_START); |
|||
JudgeResult(enRet); |
|||
enRet = Master_SendAdr(DEVICE_ADDRESS, I2C_DIR_TX); |
|||
JudgeResult(enRet); |
|||
enRet = Master_WriteData(u8TxBuf, TEST_DATA_LEN); |
|||
JudgeResult(enRet); |
|||
enRet = Master_Stop(); |
|||
JudgeResult(enRet); |
|||
|
|||
/* 5mS delay for device*/ |
|||
DDL_DelayMS(5U); |
|||
|
|||
/* I2C master data read*/ |
|||
enRet = Master_StartOrRestart(GENERATE_START); |
|||
if(1UL == TEST_DATA_LEN) |
|||
{ |
|||
I2C_AckConfig(M4_I2C1, I2C_NACK); |
|||
} |
|||
|
|||
JudgeResult(enRet); |
|||
enRet = Master_SendAdr(DEVICE_ADDRESS,I2C_DIR_RX); |
|||
JudgeResult(enRet); |
|||
enRet = Master_ReceiveAndStop(u8RxBuf, TEST_DATA_LEN); |
|||
JudgeResult(enRet); |
|||
|
|||
hc32_print("%s: i2c device id = %x\n", __func__, u8RxBuf[0]); |
|||
return OK; |
|||
} |
|||
|
|||
|
|||
/****************************************************************************
|
|||
* Name: hc32_i2cbus_initialize |
|||
* |
|||
* Description: |
|||
* Initialize one I2C bus |
|||
* |
|||
****************************************************************************/ |
|||
|
|||
FAR struct i2c_master_s *hc32_i2cbus_initialize(int port) |
|||
{ |
|||
struct hc32_i2c_priv_s * priv = NULL; |
|||
irqstate_t flags; |
|||
|
|||
/* Get I2C private structure */ |
|||
|
|||
switch (port) |
|||
{ |
|||
#ifdef CONFIG_HC32_I2C1 |
|||
case 0: |
|||
priv = (struct hc32_i2c_priv_s *)&hc32_i2c1_priv; |
|||
break; |
|||
#endif |
|||
#ifdef CONFIG_HC32_I2C2 |
|||
case 1: |
|||
priv = (struct hc32_i2c_priv_s *)&hc32_i2c2_priv; |
|||
break; |
|||
#endif |
|||
#ifdef CONFIG_HC32_I2C3 |
|||
case 2: |
|||
priv = (struct hc32_i2c_priv_s *)&hc32_i2c3_priv; |
|||
break; |
|||
#endif |
|||
default: |
|||
return NULL; |
|||
} |
|||
|
|||
/* Initialize private data for the first time, increment reference count,
|
|||
* power-up hardware and configure GPIOs. |
|||
*/ |
|||
|
|||
flags = enter_critical_section(); |
|||
|
|||
if ((volatile int)priv->refs++ == 0) |
|||
{ |
|||
hc32_i2c_sem_init(priv); |
|||
hc32_i2c_init(priv); |
|||
} |
|||
|
|||
leave_critical_section(flags); |
|||
|
|||
return (struct i2c_master_s *)priv; |
|||
} |
|||
|
|||
/****************************************************************************
|
|||
* Name: hc32_i2cbus_uninitialize |
|||
* |
|||
* Description: |
|||
* Uninitialize an I2C bus |
|||
* |
|||
****************************************************************************/ |
|||
|
|||
int hc32_i2cbus_uninitialize(FAR struct i2c_master_s *dev) |
|||
{ |
|||
FAR struct hc32_i2c_priv_s *priv = (struct hc32_i2c_priv_s *)dev; |
|||
irqstate_t flags; |
|||
|
|||
DEBUGASSERT(dev); |
|||
|
|||
/* Decrement reference count and check for underflow */ |
|||
|
|||
if (priv->refs == 0) |
|||
{ |
|||
return ERROR; |
|||
} |
|||
|
|||
flags = enter_critical_section(); |
|||
|
|||
if (--priv->refs > 0) |
|||
{ |
|||
leave_critical_section(flags); |
|||
return OK; |
|||
} |
|||
|
|||
leave_critical_section(flags); |
|||
|
|||
/* Disable power and other HW resource (GPIO's) */ |
|||
|
|||
hc32_i2c_deinit(priv); |
|||
|
|||
/* Release unused resources */ |
|||
|
|||
hc32_i2c_sem_destroy(priv); |
|||
return OK; |
|||
} |
|||
|
|||
|
|||
static void hc32_i2c_register(int bus) |
|||
{ |
|||
FAR struct i2c_master_s *i2c; |
|||
int ret; |
|||
|
|||
i2c = hc32_i2cbus_initialize(bus); |
|||
if (i2c == NULL) |
|||
{ |
|||
syslog(LOG_ERR, "Failed to get I2C%d interface\n", bus); |
|||
} |
|||
else |
|||
{ |
|||
ret = i2c_register(i2c, bus); |
|||
if (ret < 0) |
|||
{ |
|||
syslog(LOG_ERR, "Failed to register I2C%d driver: %d\n", bus, ret); |
|||
hc32_i2cbus_uninitialize(i2c); |
|||
} |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/*******************************************************************************
|
|||
* EOF (not truncated) |
|||
******************************************************************************/ |
|||
File diff suppressed because it is too large