forked from OSchip/UnityChipVerification
53 lines
1.3 KiB
Verilog
53 lines
1.3 KiB
Verilog
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module array_7_ext(
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input W0_clk,
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input [7:0] W0_addr,
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input W0_en,
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input [23:0] W0_data,
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input [3:0] W0_mask,
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input R0_clk,
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input [7:0] R0_addr,
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input R0_en,
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output [23:0] R0_data
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);
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reg reg_R0_ren;
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reg [7:0] reg_R0_addr;
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reg [23:0] ram [255:0];
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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initial begin
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#`RANDOMIZE_DELAY begin end
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for (initvar = 0; initvar < 256; initvar = initvar+1)
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ram[initvar] = {1 {$random}};
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reg_R0_addr = {1 {$random}};
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end
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`endif
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integer i;
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always @(posedge R0_clk)
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reg_R0_ren <= R0_en;
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always @(posedge R0_clk)
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if (R0_en) reg_R0_addr <= R0_addr;
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always @(posedge W0_clk)
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if (W0_en) begin
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if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0];
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if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6];
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if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12];
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if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18];
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end
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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reg [31:0] R0_random;
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`ifdef RANDOMIZE_MEM_INIT
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initial begin
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#`RANDOMIZE_DELAY begin end
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R0_random = {$random};
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reg_R0_ren = R0_random[0];
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end
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`endif
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always @(posedge R0_clk) R0_random <= {$random};
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assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0];
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`else
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assign R0_data = ram[reg_R0_addr];
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`endif
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endmodule |