forked from OSchip/llvm-project
285 lines
12 KiB
C++
285 lines
12 KiB
C++
//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// X86 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include <optional>
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namespace llvm {
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class InstCombiner;
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class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
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typedef BasicTTIImplBase<X86TTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const X86Subtarget *ST;
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const X86TargetLowering *TLI;
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const X86Subtarget *getST() const { return ST; }
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const X86TargetLowering *getTLI() const { return TLI; }
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const FeatureBitset InlineFeatureIgnoreList = {
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// This indicates the CPU is 64 bit capable not that we are in 64-bit
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// mode.
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X86::FeatureX86_64,
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// These features don't have any intrinsics or ABI effect.
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X86::FeatureNOPL,
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X86::FeatureCX16,
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X86::FeatureLAHFSAHF64,
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// Some older targets can be setup to fold unaligned loads.
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X86::FeatureSSEUnalignedMem,
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// Codegen control options.
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X86::TuningFast11ByteNOP,
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X86::TuningFast15ByteNOP,
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X86::TuningFastBEXTR,
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X86::TuningFastHorizontalOps,
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X86::TuningFastLZCNT,
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X86::TuningFastScalarFSQRT,
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X86::TuningFastSHLDRotate,
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X86::TuningFastScalarShiftMasks,
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X86::TuningFastVectorShiftMasks,
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X86::TuningFastVariableCrossLaneShuffle,
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X86::TuningFastVariablePerLaneShuffle,
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X86::TuningFastVectorFSQRT,
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X86::TuningLEAForSP,
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X86::TuningLEAUsesAG,
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X86::TuningLZCNTFalseDeps,
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X86::TuningBranchFusion,
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X86::TuningMacroFusion,
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X86::TuningPadShortFunctions,
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X86::TuningPOPCNTFalseDeps,
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X86::TuningMULCFalseDeps,
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X86::TuningPERMFalseDeps,
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X86::TuningRANGEFalseDeps,
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X86::TuningGETMANTFalseDeps,
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X86::TuningMULLQFalseDeps,
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X86::TuningSlow3OpsLEA,
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X86::TuningSlowDivide32,
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X86::TuningSlowDivide64,
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X86::TuningSlowIncDec,
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X86::TuningSlowLEA,
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X86::TuningSlowPMADDWD,
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X86::TuningSlowPMULLD,
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X86::TuningSlowSHLD,
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X86::TuningSlowTwoMemOps,
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X86::TuningSlowUAMem16,
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X86::TuningPreferMaskRegisters,
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X86::TuningInsertVZEROUPPER,
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X86::TuningUseSLMArithCosts,
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X86::TuningUseGLMDivSqrtCosts,
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// Perf-tuning flags.
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X86::TuningFastGather,
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X86::TuningSlowUAMem32,
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// Based on whether user set the -mprefer-vector-width command line.
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X86::TuningPrefer128Bit,
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X86::TuningPrefer256Bit,
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// CPU name enums. These just follow CPU string.
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X86::ProcIntelAtom
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};
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public:
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explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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/// \name Scalar TTI Implementations
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/// @{
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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/// @}
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/// \name Cache TTI Implementation
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/// @{
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std::optional<unsigned> getCacheSize(
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TargetTransformInfo::CacheLevel Level) const override;
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std::optional<unsigned> getCacheAssociativity(
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TargetTransformInfo::CacheLevel Level) const override;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(unsigned ClassID) const;
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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InstructionCost getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
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TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
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ArrayRef<int> Mask,
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TTI::TargetCostKind CostKind, int Index,
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VectorType *SubTp,
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ArrayRef<const Value *> Args = None);
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InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::CastContextHint CCH,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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CmpInst::Predicate VecPred,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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using BaseT::getVectorInstrCost;
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index);
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InstructionCost getScalarizationOverhead(VectorType *Ty,
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const APInt &DemandedElts,
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bool Insert, bool Extract);
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InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
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int VF,
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const APInt &DemandedDstElts,
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TTI::TargetCostKind CostKind);
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InstructionCost
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getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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unsigned AddressSpace, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
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const Instruction *I = nullptr);
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InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
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Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind);
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InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, bool VariableMask,
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Align Alignment,
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TTI::TargetCostKind CostKind,
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const Instruction *I);
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InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE,
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const SCEV *Ptr);
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std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const;
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std::optional<Value *>
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simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
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APInt DemandedMask, KnownBits &Known,
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bool &KnownBitsComputed) const;
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std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
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APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const;
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unsigned getAtomicMemIntrinsicMaxElementSize() const;
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InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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std::optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind);
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InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
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InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
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bool IsUnsigned,
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TTI::TargetCostKind CostKind);
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InstructionCost getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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InstructionCost getInterleavedMemoryOpCostAVX512(
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unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
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ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
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bool UseMaskForGaps = false);
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InstructionCost getIntImmCost(int64_t);
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InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind);
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind,
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Instruction *Inst = nullptr);
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InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind);
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/// Return the cost of the scaling factor used in the addressing
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/// mode represented by AM for this target, for a load/store
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/// of the specified type.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, it returns a negative value.
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InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
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int64_t BaseOffset, bool HasBaseReg,
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int64_t Scale, unsigned AddrSpace) const;
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bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
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const TargetTransformInfo::LSRCost &C2);
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bool canMacroFuseCmp();
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bool isLegalMaskedLoad(Type *DataType, Align Alignment);
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bool isLegalMaskedStore(Type *DataType, Align Alignment);
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bool isLegalNTLoad(Type *DataType, Align Alignment);
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bool isLegalNTStore(Type *DataType, Align Alignment);
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bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
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bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment);
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bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) {
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return forceScalarizeMaskedGather(VTy, Alignment);
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}
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bool isLegalMaskedGather(Type *DataType, Align Alignment);
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bool isLegalMaskedScatter(Type *DataType, Align Alignment);
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bool isLegalMaskedExpandLoad(Type *DataType);
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bool isLegalMaskedCompressStore(Type *DataType);
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bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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const SmallBitVector &OpcodeMask) const;
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bool hasDivRemOp(Type *DataType, bool IsSigned);
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bool isExpensiveToSpeculativelyExecute(const Instruction *I);
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bool isFCmpOrdCheaperThanFCmpZero(Type *Ty);
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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bool areTypesABICompatible(const Function *Caller, const Function *Callee,
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const ArrayRef<Type *> &Type) const;
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TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
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bool IsZeroCmp) const;
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bool prefersVectorizedAddressing() const;
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bool supportsEfficientVectorElementLoadStore() const;
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bool enableInterleavedAccessVectorization();
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private:
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bool supportsGather() const;
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InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
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bool VariableMask, Align Alignment,
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unsigned AddressSpace);
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InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, Align Alignment,
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unsigned AddressSpace);
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int getGatherOverhead() const;
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int getScatterOverhead() const;
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/// @}
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};
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} // end namespace llvm
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#endif
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