forked from OSchip/llvm-project
117 lines
3.4 KiB
C++
117 lines
3.4 KiB
C++
//===-- Target.cpp ----------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../Target.h"
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#include "../Latency.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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namespace llvm {
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namespace exegesis {
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#include "MipsGenExegesis.inc"
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namespace {
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class ExegesisMipsTarget : public ExegesisTarget {
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public:
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ExegesisMipsTarget() : ExegesisTarget(MipsCpuPfmCounters) {}
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private:
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std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
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const APInt &Value) const override;
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bool matchesArch(Triple::ArchType Arch) const override {
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return Arch == Triple::mips || Arch == Triple::mipsel ||
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Arch == Triple::mips64 || Arch == Triple::mips64el;
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}
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};
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} // end anonymous namespace
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// Generates instructions to load an immediate value into a register.
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static std::vector<MCInst> loadImmediate(unsigned Reg, bool IsGPR32,
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const APInt &Value) {
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unsigned ZeroReg;
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unsigned ORi, LUi, SLL;
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if (IsGPR32) {
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ZeroReg = Mips::ZERO;
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ORi = Mips::ORi;
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SLL = Mips::SLL;
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LUi = Mips::LUi;
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} else {
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ZeroReg = Mips::ZERO_64;
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ORi = Mips::ORi64;
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SLL = Mips::SLL64_64;
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LUi = Mips::LUi64;
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}
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if (Value.isIntN(16)) {
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return {MCInstBuilder(ORi)
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.addReg(Reg)
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.addReg(ZeroReg)
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.addImm(Value.getZExtValue())};
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}
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std::vector<MCInst> Instructions;
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if (Value.isIntN(32)) {
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const uint16_t HiBits = Value.getHiBits(16).getZExtValue();
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if (!IsGPR32 && Value.getActiveBits() == 32) {
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// Expand to an ORi instead of a LUi to avoid sign-extending into the
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// upper 32 bits.
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Instructions.push_back(
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MCInstBuilder(ORi)
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.addReg(Reg)
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.addReg(ZeroReg)
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.addImm(HiBits));
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Instructions.push_back(
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MCInstBuilder(SLL)
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.addReg(Reg)
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.addReg(Reg)
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.addImm(16));
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} else {
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Instructions.push_back(
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MCInstBuilder(LUi)
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.addReg(Reg)
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.addImm(HiBits));
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}
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const uint16_t LoBits = Value.getLoBits(16).getZExtValue();
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if (LoBits) {
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Instructions.push_back(
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MCInstBuilder(ORi)
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.addReg(Reg)
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.addReg(ZeroReg)
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.addImm(LoBits));
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}
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return std::move(Instructions);
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}
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llvm_unreachable("Not implemented for values wider than 32 bits");
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}
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std::vector<MCInst> ExegesisMipsTarget::setRegTo(const MCSubtargetInfo &STI,
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unsigned Reg,
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const APInt &Value) const {
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if (Mips::GPR32RegClass.contains(Reg))
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return loadImmediate(Reg, true, Value);
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if (Mips::GPR64RegClass.contains(Reg))
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return loadImmediate(Reg, false, Value);
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errs() << "setRegTo is not implemented, results will be unreliable\n";
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return {};
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}
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static ExegesisTarget *getTheExegesisMipsTarget() {
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static ExegesisMipsTarget Target;
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return &Target;
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}
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void InitializeMipsExegesisTarget() {
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ExegesisTarget::registerTarget(getTheExegesisMipsTarget());
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}
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} // namespace exegesis
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} // namespace llvm
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