forked from OSchip/llvm-project
64 lines
1.8 KiB
LLVM
64 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O1 -S < %s | FileCheck %s
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; Make sure we reassociate and1 with and2 before instcombine to allow
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; Demorgan logic fold:
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; (a & ~b) & ~c --> a & ~(b | c)
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define i4 @not_reassociate_and_and_not(i4 %a, i4 %b, i4 %c, i4 %d) {
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; CHECK-LABEL: @not_reassociate_and_and_not(
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; CHECK-NEXT: [[TMP1:%.*]] = or i4 [[B:%.*]], [[C:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = xor i4 [[TMP1]], -1
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; CHECK-NEXT: [[AND2:%.*]] = and i4 [[TMP2]], [[A:%.*]]
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; CHECK-NEXT: [[AND3:%.*]] = and i4 [[AND2]], [[D:%.*]]
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; CHECK-NEXT: ret i4 [[AND3]]
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;
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%notb = xor i4 %b, -1
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%notc = xor i4 %c, -1
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%and1 = and i4 %a, %notb
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%and2 = and i4 %and1, %d
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%and3 = and i4 %and2, %notc
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ret i4 %and3
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}
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; (a | ~b) | ~c --> a | ~(b & c)
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define i32 @not_reassociate_or_or_not(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: @not_reassociate_or_or_not(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[B:%.*]], [[C:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1
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; CHECK-NEXT: [[B2:%.*]] = or i32 [[TMP2]], [[A:%.*]]
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; CHECK-NEXT: [[B3:%.*]] = or i32 [[B2]], [[D:%.*]]
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; CHECK-NEXT: ret i32 [[B3]]
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;
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%notb = xor i32 %b, -1
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%notc = xor i32 %c, -1
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%b1 = or i32 %a, %notb
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%b2 = or i32 %b1, %d
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%b3 = or i32 %b2, %notc
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ret i32 %b3
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}
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define i32 @PR58137_sdiv(i32 %a, i32 %b) {
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; CHECK-LABEL: @PR58137_sdiv(
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; CHECK-NEXT: ret i32 [[B:%.*]]
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;
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%mul = mul nsw i32 2, %b
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%mul1 = mul nsw i32 %mul, %a
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%mul2 = mul nsw i32 2, %a
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%div = sdiv i32 %mul1, %mul2
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ret i32 %div
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}
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define i32 @PR58137_udiv(i32 %x, i32 %y) {
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; CHECK-LABEL: @PR58137_udiv(
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; CHECK-NEXT: ret i32 [[X:%.*]]
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;
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%zx = zext i32 %x to i64
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%zy = zext i32 %y to i64
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%m1 = mul nuw i64 %zx, %zy
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%m2 = mul nuw i64 4, %m1
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%m3 = mul nuw i64 4, %zy
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%d = udiv i64 %m2, %m3
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%t = trunc i64 %d to i32
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ret i32 %t
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}
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