forked from OSchip/llvm-project
96 lines
4.4 KiB
LLVM
96 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s --check-prefix=SSE
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; RUN: opt -passes="default<O3>" -S -mattr=avx < %s | FileCheck %s --check-prefix=AVX
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; This test is based on https://github.com/llvm/llvm-project/issues/50778
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; It's the unoptimized IR passed through -mem2reg to remove obvious noise.
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; This should show cooperation between instcombine, unrolling, inlining,
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; and SLP to create the target-optimal vector math+logic ops.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define noundef i64 @foo(i64 noundef %0) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 44
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; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]
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; CHECK-NEXT: ret i64 [[TMP3]]
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;
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; SSE-LABEL: @foo(
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; SSE-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 44
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; SSE-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]
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; SSE-NEXT: ret i64 [[TMP3]]
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;
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; AVX-LABEL: @foo(
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; AVX-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 44
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; AVX-NEXT: [[TMP3:%.*]] = sub nuw nsw i64 -17592186044416, [[TMP2]]
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; AVX-NEXT: ret i64 [[TMP3]]
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;
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%2 = sub i64 1048575, %0
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%3 = shl i64 %2, 44
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ret i64 %3
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}
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define void @bar(ptr noundef %0) {
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; SSE-LABEL: @bar(
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; SSE-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[TMP0:%.*]], align 8
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; SSE-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP2]], <i64 44, i64 44>
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; SSE-NEXT: [[TMP4:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP3]]
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; SSE-NEXT: store <2 x i64> [[TMP4]], ptr [[TMP0]], align 8
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; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 2
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; SSE-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
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; SSE-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[TMP6]], <i64 44, i64 44>
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; SSE-NEXT: [[TMP8:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP7]]
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; SSE-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP5]], align 8
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; SSE-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 4
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; SSE-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 8
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; SSE-NEXT: [[TMP11:%.*]] = shl <2 x i64> [[TMP10]], <i64 44, i64 44>
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; SSE-NEXT: [[TMP12:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP11]]
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; SSE-NEXT: store <2 x i64> [[TMP12]], ptr [[TMP9]], align 8
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; SSE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 6
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; SSE-NEXT: [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 8
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; SSE-NEXT: [[TMP15:%.*]] = shl <2 x i64> [[TMP14]], <i64 44, i64 44>
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; SSE-NEXT: [[TMP16:%.*]] = sub nuw nsw <2 x i64> <i64 -17592186044416, i64 -17592186044416>, [[TMP15]]
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; SSE-NEXT: store <2 x i64> [[TMP16]], ptr [[TMP13]], align 8
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; SSE-NEXT: ret void
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;
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; AVX-LABEL: @bar(
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; AVX-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr [[TMP0:%.*]], align 8
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; AVX-NEXT: [[TMP3:%.*]] = shl <4 x i64> [[TMP2]], <i64 44, i64 44, i64 44, i64 44>
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; AVX-NEXT: [[TMP4:%.*]] = sub nuw nsw <4 x i64> <i64 -17592186044416, i64 -17592186044416, i64 -17592186044416, i64 -17592186044416>, [[TMP3]]
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; AVX-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP0]], align 8
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; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 4
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; AVX-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8
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; AVX-NEXT: [[TMP7:%.*]] = shl <4 x i64> [[TMP6]], <i64 44, i64 44, i64 44, i64 44>
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; AVX-NEXT: [[TMP8:%.*]] = sub nuw nsw <4 x i64> <i64 -17592186044416, i64 -17592186044416, i64 -17592186044416, i64 -17592186044416>, [[TMP7]]
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; AVX-NEXT: store <4 x i64> [[TMP8]], ptr [[TMP5]], align 8
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; AVX-NEXT: ret void
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;
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br label %2
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2: ; preds = %12, %1
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%.0 = phi i32 [ 0, %1 ], [ %13, %12 ]
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%3 = icmp slt i32 %.0, 8
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br i1 %3, label %5, label %4
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4: ; preds = %2
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br label %14
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5: ; preds = %2
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%6 = sext i32 %.0 to i64
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%7 = getelementptr inbounds i64, ptr %0, i64 %6
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%8 = load i64, ptr %7, align 8
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%9 = call noundef i64 @foo(i64 noundef %8)
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%10 = sext i32 %.0 to i64
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%11 = getelementptr inbounds i64, ptr %0, i64 %10
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store i64 %9, ptr %11, align 8
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br label %12
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12: ; preds = %5
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%13 = add nsw i32 %.0, 1
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br label %2
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14: ; preds = %4
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ret void
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}
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