forked from OSchip/llvm-project
38 lines
1.5 KiB
LLVM
38 lines
1.5 KiB
LLVM
; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=CHECK,VF8UF1 %s
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; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=CHECK,VF8UF2 %s
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; RUN: opt -passes=loop-vectorize -force-vector-width=16 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=CHECK,VF16UF1 %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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; Check if the vector loop condition can be simplified to true for a given
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; VF/IC combination.
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define void @test_tc_less_than_16(ptr %A, i64 %N) {
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; CHECK-LABEL: define void @test_tc_less_than_16(
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; VF8UF1: [[CMP:%.+]] = icmp eq i64 %index.next, %n.vec
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; VF8UF1-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body
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;
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; VF8UF2: [[CMP:%.+]] = icmp eq i64 %index.next, %n.vec
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; VF8UF2-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body
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;
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; VF16UF1: [[CMP:%.+]] = icmp eq i64 %index.next, %n.vec
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; VF16UF1-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body
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;
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entry:
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%and = and i64 %N, 15
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br label %loop
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loop:
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%iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ]
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%p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]
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%p.src.next = getelementptr inbounds i8, ptr %p.src, i64 1
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%l = load i8, ptr %p.src, align 1
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%add = add nsw i8 %l, 10
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store i8 %add, ptr %p.src
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%iv.next = add nsw i64 %iv, -1
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%cmp = icmp eq i64 %iv.next, 0
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br i1 %cmp, label %exit, label %loop
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exit:
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ret void
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}
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