forked from OSchip/llvm-project
99 lines
2.5 KiB
LLVM
99 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
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define i32 @lshr10_and255(i32 %a) {
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; CHECK-LABEL: lshr10_and255:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.w $a0, $a0, 17, 10
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; CHECK-NEXT: ret
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%shr = lshr i32 %a, 10
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%and = and i32 %shr, 255
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ret i32 %and
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}
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define i32 @ashr20_and511(i32 %a) {
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; CHECK-LABEL: ashr20_and511:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.w $a0, $a0, 28, 20
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; CHECK-NEXT: ret
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%shr = ashr i32 %a, 20
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%and = and i32 %shr, 511
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ret i32 %and
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}
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define i32 @zext_i16_to_i32(i16 %a) {
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; CHECK-LABEL: zext_i16_to_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.w $a0, $a0, 15, 0
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; CHECK-NEXT: ret
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%res = zext i16 %a to i32
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ret i32 %res
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}
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define i32 @and8191(i32 %a) {
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; CHECK-LABEL: and8191:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.w $a0, $a0, 12, 0
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; CHECK-NEXT: ret
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%and = and i32 %a, 8191
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ret i32 %and
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}
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;; Check that andi but not bstrpick.d is generated.
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define i32 @and4095(i32 %a) {
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; CHECK-LABEL: and4095:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi $a0, $a0, 4095
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; CHECK-NEXT: ret
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%and = and i32 %a, 4095
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ret i32 %and
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}
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;; (srl (and a, 0xff0), 4) => (BSTRPICK a, 11, 4)
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define i32 @and0xff0_lshr4(i32 %a) {
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; CHECK-LABEL: and0xff0_lshr4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.w $a0, $a0, 11, 4
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; CHECK-NEXT: ret
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%and = and i32 %a, 4080
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%shr = lshr i32 %and, 4
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ret i32 %shr
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}
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;; (sra (and a, 0xff0), 5) can also be combined to (BSTRPICK a, 11, 5).
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;; This is because (sra (and a, 0xff0)) would be combined to (srl (and a, 0xff0), 5)
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;; firstly by DAGCombiner::SimplifyDemandedBits.
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define i32 @and4080_ashr5(i32 %a) {
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; CHECK-LABEL: and4080_ashr5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.w $a0, $a0, 11, 5
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; CHECK-NEXT: ret
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%and = and i32 %a, 4080
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%shr = ashr i32 %and, 5
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ret i32 %shr
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}
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;; Negative test: the second operand of AND is not a shifted mask
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define i32 @and0xf30_lshr4(i32 %a) {
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; CHECK-LABEL: and0xf30_lshr4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi $a0, $a0, 3888
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; CHECK-NEXT: srli.w $a0, $a0, 4
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; CHECK-NEXT: ret
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%and = and i32 %a, 3888
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%shr = lshr i32 %and, 4
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ret i32 %shr
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}
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;; Negative test: Shamt < MaskIdx
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define i32 @and0xff0_lshr3(i32 %a) {
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; CHECK-LABEL: and0xff0_lshr3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi $a0, $a0, 4080
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; CHECK-NEXT: srli.w $a0, $a0, 3
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; CHECK-NEXT: ret
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%and = and i32 %a, 4080
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%shr = lshr i32 %and, 3
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ret i32 %shr
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}
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