forked from OSchip/llvm-project
85 lines
4.2 KiB
YAML
85 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=greedy -o - %s | FileCheck %s
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# This testcase is restricted to use a maximum of 24 VGPRs. It is
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# therefore possible to allocate a maximum of 3 vreg_256s at a
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# time. The apparent number of registers in the class is larger, but
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# each one overlaps with the next. Allocating a vreg_64 will prevent a
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# full vreg_256 from being live at a given point.
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# The hints are trying to force allocation of overlapping vreg_256s
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# which cannot be satisfied. The last S_NOP in %bb.0 with 2 vreg_256s
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# and a vreg_64 use can be satisfied as long as the hints are ignored.
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# With the resulting allocation order, this ends up using last chance
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# recoloring for a vreg_256. We should try to recolor for completed
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# virtual registers with the same class, since the existing assignment
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# can only be corrected by adjusting to a non-overlapping register.
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--- |
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define void @recolor_impossible_hint() #0 {
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ret void
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}
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attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
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---
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---
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name: recolor_impossible_hint
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alignment: 1
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_256, preferred-register: '$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7' }
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- { id: 1, class: vreg_256, preferred-register: '$vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8' }
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- { id: 2, class: vreg_256, preferred-register: '$vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9' }
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- { id: 3, class: vreg_256, preferred-register: '$vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10' }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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occupancy: 10
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body: |
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; CHECK-LABEL: name: recolor_impossible_hint
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0, implicit-def %7, implicit-def %19, implicit-def %5
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; CHECK-NEXT: SI_SPILL_V256_SAVE %19, %stack.3, $sgpr32, 0, implicit $exec :: (store (s256) into %stack.3, align 4, addrspace 5)
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; CHECK-NEXT: SI_SPILL_V256_SAVE %7, %stack.1, $sgpr32, 0, implicit $exec :: (store (s256) into %stack.1, align 4, addrspace 5)
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; CHECK-NEXT: SI_SPILL_V256_SAVE %5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s256) into %stack.0, align 4, addrspace 5)
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; CHECK-NEXT: S_NOP 0, implicit-def %17
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; CHECK-NEXT: SI_SPILL_V256_SAVE %17, %stack.2, $sgpr32, 0, implicit $exec :: (store (s256) into %stack.2, align 4, addrspace 5)
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; CHECK-NEXT: S_NOP 0, implicit-def %4
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; CHECK-NEXT: [[SI_SPILL_V256_RESTORE:%[0-9]+]]:vreg_256 = SI_SPILL_V256_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s256) from %stack.1, align 4, addrspace 5)
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; CHECK-NEXT: [[SI_SPILL_V256_RESTORE1:%[0-9]+]]:vreg_256 = SI_SPILL_V256_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s256) from %stack.3, align 4, addrspace 5)
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; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V256_RESTORE]], implicit [[SI_SPILL_V256_RESTORE1]], implicit %4
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY [[SI_SPILL_V256_RESTORE1]]
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; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
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; CHECK-NEXT: [[SI_SPILL_V256_RESTORE2:%[0-9]+]]:vreg_256 = SI_SPILL_V256_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s256) from %stack.0, align 4, addrspace 5)
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; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V256_RESTORE2]]
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; CHECK-NEXT: [[SI_SPILL_V256_RESTORE3:%[0-9]+]]:vreg_256 = SI_SPILL_V256_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s256) from %stack.2, align 4, addrspace 5)
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; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V256_RESTORE3]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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S_NOP 0, implicit-def %0:vreg_256, implicit-def %1:vreg_256, implicit-def %2:vreg_256
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S_NOP 0, implicit-def %3:vreg_256
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S_NOP 0, implicit-def %4:vreg_64
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S_NOP 0, implicit %0, implicit %1, implicit %4
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S_CBRANCH_EXECNZ %bb.3, implicit $exec
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bb.2:
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S_NOP 0, implicit %1
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S_NOP 0, implicit %2
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S_NOP 0, implicit %3
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bb.3:
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S_ENDPGM 0
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...
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