forked from OSchip/llvm-project
26 lines
1.0 KiB
LLVM
26 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s
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; SPI_TMPRING_SIZE.WAVESIZE = 5
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; GFX10: .long 165608
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; GFX10-NEXT: .long 20480
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; SPI_TMPRING_SIZE.WAVESIZE = 17
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; GFX11: .long 165608
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; GFX11-NEXT: .long 69632
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; GCN-LABEL: {{^}}scratch_ps:
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; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0{{$}}
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; GCN-DAG: s_mov_b32 s6, -1{{$}}
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; GCN-DAG: s_mov_b32 s7, 0xe8f000
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; GCN-DAG: v_mov_b32_e32 [[V:v[0-9]+]], 2
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; GCN: buffer_store_dword [[V]], v0, s[4:7], 0 offen
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define amdgpu_ps void @scratch_ps(ptr addrspace(1) %out, i32 %in) {
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entry:
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%alloca = alloca [32 x i32], addrspace(5)
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%ptr = getelementptr [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 %in
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store volatile i32 2, ptr addrspace(5) %ptr
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ret void
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}
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