forked from OSchip/llvm-project
461 lines
16 KiB
C++
461 lines
16 KiB
C++
//===- AVRDisassembler.cpp - Disassembler for AVR ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the AVR Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "AVR.h"
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#include "AVRRegisterInfo.h"
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#include "AVRSubtarget.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "TargetInfo/AVRTargetInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "avr-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// A disassembler class for AVR.
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class AVRDisassembler : public MCDisassembler {
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public:
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AVRDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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virtual ~AVRDisassembler() = default;
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // namespace
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static MCDisassembler *createAVRDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new AVRDisassembler(STI, Ctx);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(getTheAVRTarget(),
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createAVRDisassembler);
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}
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static const uint16_t GPRDecoderTable[] = {
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AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6,
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AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,
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AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
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AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
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AVR::R28, AVR::R29, AVR::R30, AVR::R31,
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};
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static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Register = GPRDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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unsigned Register = GPRDecoderTable[RegNo + 16];
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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#include "AVRGenDisassemblerTables.inc"
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static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned addr = 0;
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addr |= fieldFromInstruction(Insn, 0, 4);
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addr |= fieldFromInstruction(Insn, 9, 2) << 4;
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unsigned reg = fieldFromInstruction(Insn, 4, 5);
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Inst.addOperand(MCOperand::createImm(addr));
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if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned addr = 0;
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addr |= fieldFromInstruction(Insn, 0, 4);
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addr |= fieldFromInstruction(Insn, 9, 2) << 4;
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unsigned reg = fieldFromInstruction(Insn, 4, 5);
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if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(addr));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned addr = fieldFromInstruction(Insn, 3, 5);
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unsigned b = fieldFromInstruction(Insn, 0, 3);
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Inst.addOperand(MCOperand::createImm(addr));
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Inst.addOperand(MCOperand::createImm(b));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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// Call targets need to be shifted left by one so this needs a custom
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// decoder.
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Inst.addOperand(MCOperand::createImm(Field << 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned d = fieldFromInstruction(Insn, 4, 5);
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if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(AVR::R31R30));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
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unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
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if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned r = fieldFromInstruction(Insn, 4, 4) * 2;
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unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;
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if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25
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unsigned k = 0;
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k |= fieldFromInstruction(Insn, 0, 4);
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k |= fieldFromInstruction(Insn, 6, 2) << 4;
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if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(k));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
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unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
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if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) ==
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MCDisassembler::Fail)
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return MCDisassembler::Fail;
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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// As in the EncoderMethod `AVRMCCodeEmitter::encodeMemri`, the memory
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// address is encoded into 7-bit, in which bits 0-5 are the immediate offset,
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// and the bit-6 is the pointer register bit (Z=0, Y=1).
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if (Insn > 127)
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return MCDisassembler::Fail;
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// Append the base register operand.
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Inst.addOperand(
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MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30));
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// Append the immediate offset operand.
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Inst.addOperand(MCOperand::createImm(Insn & 0x3f));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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// Get the register will be loaded or stored.
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unsigned RegVal = GPRDecoderTable[(Insn >> 4) & 0x1f];
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// Decode LDD/STD with offset less than 8.
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if ((Insn & 0xf000) == 0x8000) {
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unsigned RegBase = (Insn & 0x8) ? AVR::R29R28 : AVR::R31R30;
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unsigned Offset = Insn & 7; // We need not consider offset > 7.
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if ((Insn & 0x200) == 0) { // Decode LDD.
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Inst.setOpcode(AVR::LDDRdPtrQ);
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Inst.addOperand(MCOperand::createReg(RegVal));
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Inst.addOperand(MCOperand::createReg(RegBase));
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Inst.addOperand(MCOperand::createImm(Offset));
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} else { // Decode STD.
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Inst.setOpcode(AVR::STDPtrQRr);
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Inst.addOperand(MCOperand::createReg(RegBase));
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Inst.addOperand(MCOperand::createImm(Offset));
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Inst.addOperand(MCOperand::createReg(RegVal));
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}
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return MCDisassembler::Success;
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}
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// Decode the following 14 instructions. Bit 9 indicates load(0) or store(1),
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// bits 8~4 indicate the value register, bits 3-2 indicate the base address
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// register (11-X, 10-Y, 00-Z), bits 1~0 indicate the mode (00-basic,
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// 01-postinc, 10-predec).
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// ST X, Rr : 1001 001r rrrr 1100
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// ST X+, Rr : 1001 001r rrrr 1101
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// ST -X, Rr : 1001 001r rrrr 1110
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// ST Y+, Rr : 1001 001r rrrr 1001
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// ST -Y, Rr : 1001 001r rrrr 1010
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// ST Z+, Rr : 1001 001r rrrr 0001
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// ST -Z, Rr : 1001 001r rrrr 0010
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// LD Rd, X : 1001 000d dddd 1100
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// LD Rd, X+ : 1001 000d dddd 1101
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// LD Rd, -X : 1001 000d dddd 1110
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// LD Rd, Y+ : 1001 000d dddd 1001
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// LD Rd, -Y : 1001 000d dddd 1010
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// LD Rd, Z+ : 1001 000d dddd 0001
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// LD Rd, -Z : 1001 000d dddd 0010
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if ((Insn & 0xfc00) != 0x9000 || (Insn & 0xf) == 0)
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return MCDisassembler::Fail;
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// Get the base address register.
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unsigned RegBase;
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switch (Insn & 0xc) {
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case 0xc:
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RegBase = AVR::R27R26;
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break;
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case 0x8:
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RegBase = AVR::R29R28;
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break;
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case 0x0:
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RegBase = AVR::R31R30;
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break;
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default:
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return MCDisassembler::Fail;
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}
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// Set the opcode.
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switch (Insn & 0x203) {
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case 0x200:
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Inst.setOpcode(AVR::STPtrRr);
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Inst.addOperand(MCOperand::createReg(RegBase));
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Inst.addOperand(MCOperand::createReg(RegVal));
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return MCDisassembler::Success;
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case 0x201:
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Inst.setOpcode(AVR::STPtrPiRr);
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break;
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case 0x202:
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Inst.setOpcode(AVR::STPtrPdRr);
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break;
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case 0:
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Inst.setOpcode(AVR::LDRdPtr);
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Inst.addOperand(MCOperand::createReg(RegVal));
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Inst.addOperand(MCOperand::createReg(RegBase));
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return MCDisassembler::Success;
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case 1:
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Inst.setOpcode(AVR::LDRdPtrPi);
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break;
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case 2:
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Inst.setOpcode(AVR::LDRdPtrPd);
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break;
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default:
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return MCDisassembler::Fail;
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}
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// Build postinc/predec machine instructions.
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if ((Insn & 0x200) == 0) { // This is a load instruction.
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Inst.addOperand(MCOperand::createReg(RegVal));
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Inst.addOperand(MCOperand::createReg(RegBase));
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Inst.addOperand(MCOperand::createReg(RegBase));
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} else { // This is a store instruction.
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Inst.addOperand(MCOperand::createReg(RegBase));
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Inst.addOperand(MCOperand::createReg(RegBase));
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Inst.addOperand(MCOperand::createReg(RegVal));
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// STPtrPiRr and STPtrPdRr have an extra immediate operand.
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Inst.addOperand(MCOperand::createImm(1));
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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if (Bytes.size() < 2) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Size = 2;
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Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
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return MCDisassembler::Success;
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}
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static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Size = 4;
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Insn =
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(Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
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return MCDisassembler::Success;
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}
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static const uint8_t *getDecoderTable(uint64_t Size) {
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switch (Size) {
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case 2:
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return DecoderTable16;
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case 4:
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return DecoderTable32;
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default:
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llvm_unreachable("instructions must be 16 or 32-bits");
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}
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}
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DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &CStream) const {
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uint32_t Insn;
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DecodeStatus Result;
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// Try decode a 16-bit instruction.
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{
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Result = readInstruction16(Bytes, Address, Size, Insn);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Try to auto-decode a 16-bit instruction.
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Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail)
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return Result;
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// Try to decode to a load/store instruction. ST/LD need a specified
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// DecoderMethod, as they already have a specified PostEncoderMethod.
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Result = decodeLoadStore(Instr, Insn, Address, this);
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if (Result != MCDisassembler::Fail)
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return Result;
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}
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// Try decode a 32-bit instruction.
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{
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Result = readInstruction32(Bytes, Address, Size, Insn);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address,
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this, STI);
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|
if (Result != MCDisassembler::Fail) {
|
|
return Result;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
}
|
|
|
|
typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
|
|
const MCDisassembler *Decoder);
|