forked from OSchip/llvm-project
410 lines
14 KiB
C++
410 lines
14 KiB
C++
//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#include "AArch64FrameLowering.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64SelectionDAGInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "AArch64GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class Triple;
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class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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public:
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enum ARMProcFamilyEnum : uint8_t {
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Others,
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A64FX,
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Ampere1,
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AppleA7,
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AppleA10,
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AppleA11,
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AppleA12,
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AppleA13,
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AppleA14,
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AppleA15,
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AppleA16,
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Carmel,
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CortexA35,
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CortexA53,
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CortexA55,
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CortexA510,
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CortexA57,
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CortexA65,
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CortexA72,
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CortexA73,
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CortexA75,
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CortexA76,
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CortexA77,
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CortexA78,
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CortexA78C,
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CortexA710,
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CortexA715,
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CortexR82,
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CortexX1,
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CortexX1C,
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CortexX2,
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CortexX3,
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ExynosM3,
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Falkor,
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Kryo,
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NeoverseE1,
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NeoverseN1,
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NeoverseN2,
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Neoverse512TVB,
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NeoverseV1,
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NeoverseV2,
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Saphira,
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ThunderX2T99,
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ThunderX,
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ThunderXT81,
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ThunderXT83,
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ThunderXT88,
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ThunderX3T110,
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TSV110
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};
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protected:
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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ARMProcFamilyEnum ARMProcFamily = Others;
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// Enable 64-bit vectorization in SLP.
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unsigned MinVectorRegisterBitWidth = 64;
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// Bool members corresponding to the SubtargetFeatures defined in tablegen
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "AArch64GenSubtargetInfo.inc"
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uint8_t MaxInterleaveFactor = 2;
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uint8_t VectorInsertExtractBaseCost = 3;
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uint16_t CacheLineSize = 0;
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uint16_t PrefetchDistance = 0;
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uint16_t MinPrefetchStride = 1;
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unsigned MaxPrefetchIterationsAhead = UINT_MAX;
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unsigned PrefFunctionLogAlignment = 0;
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unsigned PrefLoopLogAlignment = 0;
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unsigned MaxBytesForLoopAlignment = 0;
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unsigned MaxJumpTableSize = 0;
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// ReserveXRegister[i] - X#i is not available as a general purpose register.
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BitVector ReserveXRegister;
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// ReserveXRegisterForRA[i] - X#i is not available for register allocator.
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BitVector ReserveXRegisterForRA;
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// CustomCallUsedXRegister[i] - X#i call saved.
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BitVector CustomCallSavedXRegs;
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bool IsLittle;
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bool StreamingSVEModeDisabled;
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unsigned MinSVEVectorSizeInBits;
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unsigned MaxSVEVectorSizeInBits;
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unsigned VScaleForTuning = 2;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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AArch64FrameLowering FrameLowering;
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AArch64InstrInfo InstrInfo;
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AArch64SelectionDAGInfo TSInfo;
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AArch64TargetLowering TLInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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private:
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/// initializeSubtargetDependencies - Initializes using CPUString and the
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/// passed in feature string so that we can use initializer lists for
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/// subtarget initialization.
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AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString,
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StringRef TuneCPUString);
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/// Initialize properties based on the selected processor family.
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void initializeProperties();
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &TuneCPU, const std::string &FS,
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const TargetMachine &TM, bool LittleEndian,
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unsigned MinSVEVectorSizeInBitsOverride = 0,
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unsigned MaxSVEVectorSizeInBitsOverride = 0,
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bool StreamingSVEModeDisabled = true);
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// Getters for SubtargetFeatures defined in tablegen
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool GETTER() const { return ATTRIBUTE; }
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#include "AArch64GenSubtargetInfo.inc"
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const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const AArch64FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const AArch64TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const AArch64RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const CallLowering *getCallLowering() const override;
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const InlineAsmLowering *getInlineAsmLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool enableMachineScheduler() const override { return true; }
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bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
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/// Returns ARM processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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ARMProcFamilyEnum getProcFamily() const {
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return ARMProcFamily;
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}
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bool isXRaySupported() const override { return true; }
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unsigned getMinVectorRegisterBitWidth() const {
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// Don't assume any minimum vector size when PSTATE.SM may not be 0.
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if (!isStreamingSVEModeDisabled())
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return 0;
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return MinVectorRegisterBitWidth;
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}
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bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
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bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
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unsigned getNumXRegisterReserved() const {
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BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
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AllReservedX |= ReserveXRegister;
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AllReservedX |= ReserveXRegisterForRA;
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return AllReservedX.count();
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}
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bool isXRegCustomCalleeSaved(size_t i) const {
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return CustomCallSavedXRegs[i];
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}
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bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
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/// Return true if the CPU supports any kind of instruction fusion.
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bool hasFusion() const {
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return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
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hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
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hasFuseAdrpAdd() || hasFuseLiterals();
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}
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unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
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unsigned getVectorInsertExtractBaseCost() const;
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unsigned getCacheLineSize() const override { return CacheLineSize; }
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unsigned getPrefetchDistance() const override { return PrefetchDistance; }
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unsigned getMinPrefetchStride(unsigned NumMemAccesses,
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unsigned NumStridedMemAccesses,
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unsigned NumPrefetches,
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bool HasCall) const override {
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return MinPrefetchStride;
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}
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unsigned getMaxPrefetchIterationsAhead() const override {
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return MaxPrefetchIterationsAhead;
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}
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unsigned getPrefFunctionLogAlignment() const {
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return PrefFunctionLogAlignment;
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}
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unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
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unsigned getMaxBytesForLoopAlignment() const {
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return MaxBytesForLoopAlignment;
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}
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unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
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/// CPU has TBI (top byte of addresses is ignored during HW address
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/// translation) and OS enables it.
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bool supportsAddressTopByteIgnored() const;
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bool isLittleEndian() const { return IsLittle; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetIOS() const { return TargetTriple.isiOS(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
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bool isWindowsArm64EC() const { return TargetTriple.isWindowsArm64EC(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isTargetILP32() const {
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return TargetTriple.isArch32Bit() ||
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TargetTriple.getEnvironment() == Triple::GNUILP32;
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}
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bool useAA() const override;
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bool addrSinkUsingGEPs() const override {
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// Keeping GEPs inbounds is important for exploiting AArch64
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// addressing-modes in ILP32 mode.
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return useAA() || isTargetILP32();
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}
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bool useSmallAddressing() const {
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switch (TLInfo.getTargetMachine().getCodeModel()) {
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case CodeModel::Kernel:
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// Kernel is currently allowed only for Fuchsia targets,
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// where it is the same as Small for almost all purposes.
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case CodeModel::Small:
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return true;
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default:
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return false;
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}
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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/// ClassifyGlobalReference - Find the target operand flags that describe
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/// how a global value should be referenced for the current subtarget.
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unsigned ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const;
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unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
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const TargetMachine &TM) const;
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/// This function is design to compatible with the function def in other
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/// targets and escape build error about the virtual function def in base
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/// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
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unsigned char
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classifyGlobalFunctionReference(const GlobalValue *GV) const override {
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return 0;
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}
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const override;
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bool enableEarlyIfConversion() const override;
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std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
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bool isCallingConvWin64(CallingConv::ID CC) const {
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switch (CC) {
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case CallingConv::C:
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case CallingConv::Fast:
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case CallingConv::Swift:
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return isTargetWindows();
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case CallingConv::Win64:
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return true;
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default:
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return false;
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}
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}
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/// Return whether FrameLowering should always set the "extended frame
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/// present" bit in FP, or set it based on a symbol in the runtime.
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bool swiftAsyncContextIsDynamicallySet() const {
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// Older OS versions (particularly system unwinders) are confused by the
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// Swift extended frame, so when building code that might be run on them we
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// must dynamically query the concurrency library to determine whether
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// extended frames should be flagged as present.
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const Triple &TT = getTargetTriple();
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unsigned Major = TT.getOSVersion().getMajor();
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switch(TT.getOS()) {
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default:
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return false;
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case Triple::IOS:
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case Triple::TvOS:
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return Major < 15;
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case Triple::WatchOS:
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return Major < 8;
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case Triple::MacOSX:
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case Triple::Darwin:
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return Major < 12;
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}
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}
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void mirFileLoaded(MachineFunction &MF) const override;
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bool hasSVEorSME() const { return hasSVE() || hasSME(); }
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// Return the known range for the bit length of SVE data registers. A value
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// of 0 means nothing is known about that particular limit beyong what's
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// implied by the architecture.
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unsigned getMaxSVEVectorSizeInBits() const {
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assert(hasSVEorSME() &&
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"Tried to get SVE vector length without SVE support!");
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return MaxSVEVectorSizeInBits;
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}
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unsigned getMinSVEVectorSizeInBits() const {
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assert(hasSVEorSME() &&
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"Tried to get SVE vector length without SVE support!");
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return MinSVEVectorSizeInBits;
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}
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bool useSVEForFixedLengthVectors() const {
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if (forceStreamingCompatibleSVE())
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return true;
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// Prefer NEON unless larger SVE registers are available.
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return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
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}
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bool forceStreamingCompatibleSVE() const;
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unsigned getVScaleForTuning() const { return VScaleForTuning; }
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const char* getChkStkName() const {
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if (isWindowsArm64EC())
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return "__chkstk_arm64ec";
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return "__chkstk";
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}
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const char* getSecurityCheckCookieName() const {
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if (isWindowsArm64EC())
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return "__security_check_cookie_arm64ec";
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return "__security_check_cookie";
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}
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bool isStreamingSVEModeDisabled() const { return StreamingSVEModeDisabled; }
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};
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} // End llvm namespace
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#endif
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