forked from OSchip/llvm-project
140 lines
8.2 KiB
C++
140 lines
8.2 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
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// RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
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// expected-no-diagnostics
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struct S {
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int a, b;
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};
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struct P {
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int a, b;
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};
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// CHECK-LABEL: @_Z6simplePfS_Pi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 4
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// CHECK-NEXT: [[P:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[PP:%.*]] = alloca [[STRUCT_P:%.*]], align 4
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// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
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// CHECK-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
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// CHECK-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
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// CHECK-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
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// CHECK-NEXT: [[DOTCOUNT_ADDR10:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
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// CHECK-NEXT: store ptr [[B:%.*]], ptr [[B_ADDR]], align 8
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// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8
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// CHECK-NEXT: store i32 3, ptr [[I]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
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// CHECK-NEXT: store ptr [[I]], ptr [[TMP0]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
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// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4
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// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4
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// CHECK-NEXT: call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
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// CHECK-NEXT: [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
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// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
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// CHECK: omp_loop.preheader:
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER:%.*]]
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// CHECK: omp_loop.header:
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// CHECK-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
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// CHECK-NEXT: br label [[OMP_LOOP_COND:%.*]]
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// CHECK: omp_loop.cond:
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// CHECK-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]]
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// CHECK-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
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// CHECK: omp_loop.body:
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// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED1]]), !llvm.access.group [[ACC_GRP3:![0-9]+]]
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// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 [[IDXPROM]]
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// CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i32 0, i32 0
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// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[A2]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to float
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// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP5]], [[CONV]]
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// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[P]], align 8, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP7]], i32 0, i32 0
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// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP8]] to float
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// CHECK-NEXT: [[ADD5:%.*]] = fadd float [[ADD]], [[CONV4]]
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// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP10]] to i64
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// CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM6]]
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// CHECK-NEXT: store float [[ADD5]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: br label [[OMP_LOOP_INC]]
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// CHECK: omp_loop.inc:
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// CHECK-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
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// CHECK: omp_loop.exit:
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// CHECK-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
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// CHECK: omp_loop.after:
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// CHECK-NEXT: store i32 3, ptr [[J]], align 4
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// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED8]], i32 0, i32 0
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// CHECK-NEXT: store ptr [[J]], ptr [[TMP11]], align 8
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// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED9]], i32 0, i32 0
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// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4
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// CHECK-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
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// CHECK-NEXT: call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR10]], ptr [[AGG_CAPTURED8]])
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// CHECK-NEXT: [[DOTCOUNT11:%.*]] = load i32, ptr [[DOTCOUNT_ADDR10]], align 4
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// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER12:%.*]]
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// CHECK: omp_loop.preheader12:
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER13:%.*]]
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// CHECK: omp_loop.header13:
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// CHECK-NEXT: [[OMP_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER12]] ], [ [[OMP_LOOP_NEXT21:%.*]], [[OMP_LOOP_INC16:%.*]] ]
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// CHECK-NEXT: br label [[OMP_LOOP_COND14:%.*]]
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// CHECK: omp_loop.cond14:
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// CHECK-NEXT: [[OMP_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_LOOP_IV19]], [[DOTCOUNT11]]
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// CHECK-NEXT: br i1 [[OMP_LOOP_CMP20]], label [[OMP_LOOP_BODY15:%.*]], label [[OMP_LOOP_EXIT17:%.*]]
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// CHECK: omp_loop.body15:
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// CHECK-NEXT: call void @__captured_stmt.3(ptr [[J]], i32 [[OMP_LOOP_IV19]], ptr [[AGG_CAPTURED9]]), !llvm.access.group [[ACC_GRP8:![0-9]+]]
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// CHECK-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_P]], ptr [[PP]], i32 0, i32 0
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// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[A22]], align 4, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP16]] to i64
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// CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 [[IDXPROM23]]
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// CHECK-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX24]], align 4, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: br label [[OMP_LOOP_INC16]]
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// CHECK: omp_loop.inc16:
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// CHECK-NEXT: [[OMP_LOOP_NEXT21]] = add nuw i32 [[OMP_LOOP_IV19]], 1
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER13]], !llvm.loop [[LOOP9:![0-9]+]]
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// CHECK: omp_loop.exit17:
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// CHECK-NEXT: br label [[OMP_LOOP_AFTER18:%.*]]
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// CHECK: omp_loop.after18:
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// CHECK-NEXT: ret void
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//
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void simple(float *a, float *b, int *c) {
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S s, *p;
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P pp;
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#pragma omp simd safelen(3) order(concurrent)
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for (int i = 3; i < 32; i += 5) {
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a[i] = b[i] + s.a + p->a;
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}
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#pragma omp simd
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for (int j = 3; j < 32; j += 5) {
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c[j] = pp.a;
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}
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}
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//.
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// CHECK: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
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// CHECK: attributes #1 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
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//.
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// CHECK: !0 = !{i32 1, !"wchar_size", i32 4}
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// CHECK: !1 = !{i32 7, !"openmp", i32 50}
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// CHECK: !3 = distinct !{}
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// CHECK: !4 = distinct !{!4, !5, !6, !7}
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// CHECK: !5 = !{!"llvm.loop.parallel_accesses", !3}
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// CHECK: !6 = !{!"llvm.loop.vectorize.enable", i1 true}
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// CHECK: !7 = !{!"llvm.loop.vectorize.width", i32 3}
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// CHECK: !8 = distinct !{}
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// CHECK: !9 = distinct !{!9, !10, !6}
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// CHECK: !10 = !{!"llvm.loop.parallel_accesses", !8}
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//.
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