maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
444,543 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

164595 Commits

Author SHA1 Message Date
zhoujingya 319e10771e [VENTUS][fix] Add `.rodata.ventus.resource` in linker script 2023-09-15 16:41:21 +08:00
zhoujingya dc3ffe70cf [VENTUS][fix] Fix getStackSize calculation bugs 2023-09-14 15:52:08 +08:00
zhoujingya 0e5eef6abb [VENTUS][fix] fix add instruction 
Summary:
fix addi instruction, there will be a hardware error when immediate is
negative number.

Test Plan: fix add instruction

Reviewers: zhoujing

Subscribers: zhoujing

Differential Revision: http://www.tpt.com/D722

Signed-off-by: qinfan <qinfan.wang@terapines.com>
 2023-09-08 10:32:17 +08:00
zhoujingya 2e292191ae
Merge pull request #11 from THU-DSP-LAB/dev 2023-09-08 09:43:11 +08:00
zhoujingya 6faba77dc3 [VENTUS][NFC] Update comments 2023-09-07 22:18:13 +08:00
zhoujingya c25d00552c [VENTUS][fix] Legalize vlw12.v instruction for variadic functions 2023-09-07 16:39:11 +08:00
zhoujingya b7b8fa50ba [VENTUS][fix] Fix load instruction selection pattern for vastart 
In standard riscv vararg support, the varstart frame index will be stored in stack,
but because if the design of ventus, some code generation  will be like this
        vlw.v   v0, -44(v8)
        vadd.vi v1, v0, 4
        vsw.v   v1, -44(v8)
        \vlw12.v v0, 0(v0)
the last vlw12 instruction is actually illeagl, it should be vlw
 2023-09-05 14:41:10 +08:00
zhoujingya 649f4da46a [VENTUS][fix] Fix load instruction selection pattern for vastart 
In standard riscv vararg support, the varstart frame index will be stored in stack,
but because if the design of ventus, some code generation  will be like this
        vlw.v   v0, -44(v8)
        vadd.vi v1, v0, 4
        vsw.v   v1, -44(v8)
        \vlw12.v v0, 0(v0)
the last vlw12 instruction is actually illeagl, it should be vlw
 2023-09-05 11:15:53 +08:00
zhoujing 6491bdfb02 Revert "[VENTUS][fix] No need to spill/restore callee saved registers for kernel function" 
This reverts commit 85df9000bb.
 2023-08-27 15:47:26 +08:00
zhoujing 2d8205dd54 [VENTUS][fix] Kernel function arguments are not divergent path 2023-08-21 16:14:21 +08:00
zhoujing 85df9000bb [VENTUS][fix] No need to spill/restore callee saved registers for kernel function 2023-08-21 14:44:45 +08:00
zhoujing 826c4cb599 Revert "[VENTUS][fix] Insert barrier instruction for function calling" 
This reverts commit 7e4b7a6ae1.
 2023-08-16 14:50:42 +08:00
zhoujing 63911b8554 [VENTUS][fix] fix operand order bugs in ternary operands instructions 
Previous commit changed the order of operands in some three operands instructions, 09b6c28686
 2023-08-15 13:53:13 +08:00
qinfan 09b6c28686 [VENTUS][fix]Fix Instruction errors and add test files 
1.Fix errors in VALUrVV class(llvm/lib/Target/RISCV/VentusInstrInfoV.td) where two source operand positions were reversed,
this is differnt from the conventional RISCV instruction.
2.Fix errors in VALUrVF class, same as above.
3.The instructions associated with the above two errors are "vfnmadd.vv", "vfnmadd.vf", etc.
4.Add MC level FileCheck test files to test V instructions.
 2023-08-11 17:27:47 +08:00
zhoujing 700020da1e [VENTUS][fix] Fix vastart builtin codegen 2023-08-09 17:07:15 +08:00
zhoujing 499956ea8d [VENTUS][fix] Change private memory base register to v8 register for variadic function 2023-08-08 17:58:18 +08:00
zhoujing 198eea9938 [VENTUS][feat] Support varadic function && enable address space in vastart/vaend 2023-08-08 15:45:41 +08:00
zhoujing 50b23dc21a [VENTUS][fix] Deprecating vmv.s.x and use vmv.v.x instead 
As required, vmv.s.x instruction may will later be deprecated
 2023-08-01 13:25:24 +08:00
zhoujing 592d77cb76 [VENTUS][fix] Add vmslt(u)/vmsge(u) instructions' alias 
Based on vspec-doc(https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc)
ans Ventus design documentation
 2023-08-01 13:06:49 +08:00
zhoujing f995792016 [VENTUS][test] Add resource usage information test file 2023-08-01 09:19:46 +08:00
zhoujing 229a1f95fb [VENTUS][fix] Disable vmslt.vi instruction codegen 2023-07-31 13:54:09 +08:00
zhoujing 7e4b7a6ae1 [VENTUS][fix] Insert barrier instruction for function calling 
Stack space is shared between different warps, if two warps are executing
different functions, then the access to the return address will conflict,
which will lead the warp executing faster can not find the return address,
so we would like to add a barrier instruction after the lw and before the ret,
to ensure that the warps have the same scope of the sp pointer
 2023-07-31 11:01:14 +08:00
zhoujing 98474922a4 [VENTUS][fix] Add LDS/PDS calculation 
Later need to fix the local data declaration calculation
 2023-07-27 11:58:31 +08:00
zhoujing 0780087477 [VENTUS][RISCV][fix] Fix the register usage calculation of VGPR/GPR 2023-07-26 17:31:13 +08:00
zhoujing 9d56abe113 [VENTUS][RISCV][NFC] Add comment && Typo fix 2023-07-25 10:33:34 +08:00
zhoujing 1df9e6cdae [VENTUS][RISCV][feat] Initialize adding ventus resource usage information to ELF file 2023-07-25 10:22:33 +08:00
zhoujing dbdb0cbdfa [VENTUS][RISCV][feat] Add API to calculate VGPR/SGPR register usage information 2023-07-24 17:27:42 +08:00
zhoujing 1df9b6223c [VENTUS][RISCV][feat] Add atomic instructions VGPR index support 2023-07-24 13:38:42 +08:00
zhoujing 4a74fa2d0c [VENTUS][RISCV][feat] Add findUnusedRegister function in RISCVRegisterInfo 2023-07-24 13:02:26 +08:00
zhoujing 623ca8b4ba [VENTUS][RISCV][fix] Fix stack size calculation bug 2023-07-21 18:02:33 +08:00
zhoujing 3719c07dc0 [VENTUS][RISCV][fix] Modify JOIN instruction to use X0 rather than V0 2023-07-13 17:01:36 +08:00
zhoujing a9d1e6f524 [VENTUS][RISCV][fix] Avoid MBB label lost after optimization 2023-07-13 13:26:13 +08:00
zhoujing e6ae0f7ac6 [VENTUS][RISCV][fix] Disable simple loop optimization to call llvm memset/memcpy intrinsics 2023-07-11 16:26:49 +08:00
zhoujing 77c0b15cff [VENTUS][RISCV][test&fix] Add more MC test and fix related bugs 2023-07-11 11:17:55 +08:00
zhoujing e7b96af8fa [VENTUS][RISCV][test] Add MC test for ventus customized instructions 2023-07-10 16:27:50 +08:00
zhoujing b2d9d1f535 [VENTUS][RISCV][fix] Disable all widening vector arithmetic instructions codegen 2023-07-10 10:47:53 +08:00
yanming 4c099fb3d5 [VENTUS][RISCV] Move `regext insertion pass` after `insert join instruction pass`. 2023-07-07 17:22:27 +08:00
yanming d37e92610d [VENTUS][RISCV] Remove redundant code and enable regext insertion pass when verify machineinstrs. 2023-07-07 17:08:42 +08:00
zhoujing 7da8486eb3 [VENTUS][RISCV][feat] Add data structure interface for collecting ventus program information 2023-07-07 15:42:25 +08:00
zhoujing 4fea917aec [VENTUS][RISCV][fix] Fix pattern match errors 2023-07-07 13:48:55 +08:00
yanming c0b7829a87 [VENTUS][RISCV] Skip TargetOpcode::KILL instruction in regext insertion pass. 2023-07-07 13:46:12 +08:00
yanming f5df45650f [VENTUS][RISCV] Fix private memory load/store instructions definitions. 2023-07-07 11:12:24 +08:00
yanming e2ef54c16b [VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass. 
Summary: Encoding register ordering in tablegen.

Test Plan: llvm/test/CodeGen/RISCV/VentusGPGPU/builtin-noverify.ll

Reviewers: zhoujing, hualin

Reviewed By: zhoujing

Differential Revision: http://www.tpt.com/D638
 2023-07-06 11:47:34 +08:00
yanming 4a12b19a74 Revert "Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0)" 
This reverts commit 625746818d.
 2023-07-03 11:58:37 +08:00
yanming db2c4417fb [VENTUS][RISC][NFC] Use getAnalysis to get MachinePostDominatorTree. 2023-07-03 10:33:45 +08:00
yanming 41564530d5 [VENTUS][RISCV][Fix] Add PseudoBR when converge return bb in InsertJoinToVBranch pass. 2023-06-30 12:21:50 +08:00
yanming fe3244b577 [VENTUS][RISCV] Fix a bug in InsertJoinToVBranch pass. 2023-06-30 11:45:23 +08:00
yanming a5c8b18ce3 [VENTUS][RISCV] Fix setrpc instruction definition, use auipc + setrpc to set rpc. 
It is able to solve address ranges to [-2^31, 2^31).
 2023-06-30 11:26:58 +08:00
zhoujing 56fe569090 [VENTUS][RISCV][NFC] Disable conversion for floating VV instrcution convertion 
The copy is desired to be from GPRF32, but all the cases are from GPR, so we
disable related instruction conversion
 2023-06-29 14:28:02 +08:00
zhoujing 24dbcd9b0e [VENTUS][RISCV][NFC] Define interfaces for VENTUS 
Our previous design has two stacks, TP&SP, but we only need to store ra to sp,
and restore it from sp, this make it inconvenient to calculate stack offset for
two stack frame offset,  Here we just define interfaces, but we do not really
implement it, if needed, we need to remove callee saved registers, and modify
the related overrided functions
 2023-06-28 11:19:29 +08:00
yanming 137ae78ebe [VENTUS][RISCV] Move VentusRegextInsertionPass and VentusInsertJoinToVBranchPass before BranchRelaxationPass. 2023-06-28 11:04:47 +08:00
yanming 81c652183c [VENTUS][RISCV][fix] Delete source pseudo instruction in expandBarrier. 2023-06-27 16:27:11 +08:00
yanming 5ceac7f7a1 [VENTUS][RISCV] Fix insert setrpc/join instruction pass for VBranch. 2023-06-27 16:02:01 +08:00
zhoujing bfed578a87 [VENTUS][RISCV][fix] Fix illegal vmv instruction in libclc library 
Other than atomic functions library, there are no illegal instructions

Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-06-27 15:53:51 +08:00
yanming 7f38ea8deb [VENTUS][RISCV] Clean divergent branch analysis. 2023-06-27 14:21:24 +08:00
zhoujing d48134f86e [VENTUS][RISCV][fix] Add divergent analysis for function arguments 2023-06-27 11:44:50 +08:00
yanming 58ce5c83b8 [VENTUS][RISCV] Fix VBranch instruction info and select codegen patterns. 2023-06-27 11:12:37 +08:00
yanming df97b38340 [Ventus][RISCV] Disable insert join instruction pass. 2023-06-27 10:08:02 +08:00
zhoujing 1110ae0242 [VENTUS][RISCV][fix] Fix illegal vmv instruction for ISD::SRL SDNode 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-06-26 22:08:25 +08:00
yanming 6189c2e9e7 [VENTUS][RISCV] Add SETRPC and JOIN instruction definition. 2023-06-26 15:40:37 +08:00
zhoujing 14e9011074 [VENTUS][RISCV][fix] Add divergent pattern for floating instructions 
We just simply add zfinx support for floating instrionctions before,
now we add divergent analysis here to avoid illegal VGPR move to GPRF32
 2023-06-26 15:09:14 +08:00
zhoujing 7b8402802a [VENTUS][RISCV][fix] Fix calling convention 2023-06-25 22:03:04 +08:00
zhoujing f494e20d44 [VENTUS][RISCV][fix] Fix private memory access instructions' codegen errors 
We changed the private memory access' encoding in this commit `6da666856b`,
this commit is to fix the codegen bugs by that commit
 2023-06-25 10:59:21 +08:00
Aries e6b7935c89 [Ventus] ABI and stack adjustment. 
Remove all SGPRs(except ra) from callee saved register set, as they are mainly used in kernel function.
Unify the stack to use TP only, we will emit customized instructions for SP use which should not be
considered as stack according to LLVM codegen infrastructure(only 1 stack is allowed).
By unifying the stack to TP based, it is much easiler for the backend codegen.
 2023-06-21 13:08:02 +08:00
zhoujing a6e8ff959a [VENTUS][RISCV][fix] Add missing flags for building libclc 
The flags information are lost by previous merge commit `Merge libclc-vector-support`
 2023-06-21 10:59:48 +08:00
zhoujing 384651ceac [VENTUS][RISCV][fix] Fix vsetvli instruction's encoding 2023-06-21 10:16:03 +08:00
zhoujing 615705a6c6 [VENTUS][RISCV][fix] Fix calling convention 2023-06-19 17:21:04 +08:00
Aries a7b9ee473b [NFC] Fix comment style 2023-06-19 13:14:31 +08:00
Aries 6da666856b [Ventus] Fix design bug, redesign vlw.v/vsw.v to use vGPR as base address instead of using sGPR. 2023-06-19 12:59:43 +08:00
zhoujingya b438e64b66 Merge branch 'dev-ventus' 2023-06-16 17:51:00 +08:00
zhoujing 513412bb33 [VENTUS][RISCV][fix] Fix building libclc errors 2023-06-16 17:42:22 +08:00
yanming 6b0a28390e [VENTUS][RISCV][fix] Fix build warning 2023-06-16 10:25:02 +08:00
zhoujing 6636793f64 Merge libclc-vector-support 2023-06-16 09:41:08 +08:00
zhoujing 2c5cbdd187 [VENTUS][RISCV][fix] Add more divergence ananlysis 
Referenced from AMDGPU
 2023-06-15 22:34:40 +08:00
zhoujing c30c837caa [VENTUS][RISCV][fix] Fix SP stack size calculation error 2023-06-15 18:12:34 +08:00
zhoujing e54daab265 [VENTUS][RISCV][fix] Fix function call calling convention 2023-06-15 13:36:12 +08:00
zhoujing e10ff3b94d Merge branch 'main' into dev-ventus 2023-06-15 12:19:17 +08:00
Aries bc5d0f6024 Avoiding generating VGPR to SGPR copy for CopyFromReg. 2023-06-15 09:30:22 +08:00
zhoujing 53a932e665 [VENTUS][RISCV][fix] Modify calling convention for non-kernel function arguments based on private memory address 
In our previous calling convention design, all non-kernel arguments are passed
by VGPRS or TP stack, but when the arguments point to private memory address
space, the wrong memory access instructions will be generated, because private
memory based address is scalar register
 2023-06-14 21:26:53 +08:00
zhoujing 70ca64bbc8 [VENTUS][RISCV][fix] Add more load/store opcode for stack spill action 2023-06-14 11:12:37 +08:00
zhoujing e5e7a0047a [VENTUS][RISCV][fix] Fix local memory access error in kernel function 2023-06-12 16:22:45 +08:00
zhoujing 940da111a3 [VENTUS][RISCV][fix] Fix divergent analysis bug for store node 2023-06-12 14:50:55 +08:00
zhoujing c60810b243 [VENTUS][RISCV][feat] Modify SP stack size calculation 
Add initial SP stack size calculation support, still remains many issues
 2023-06-12 13:27:55 +08:00
zhoujing faf6a0bcd9 [VENTUS][RISCV][fix] Add initial Tp stack size calculation 
Cause there are two stacks in Ventus, we need to seperate TP stack and SP stack,
this commit just add very initial support for TP stack size calculation
 2023-06-11 12:18:39 +08:00
zhoujing 180b3d4429 [VENTUS][RISCV][feat] Add VGPRSpill stack id for ventus 
There are two stacks in ventus for registers spill, SGPRSpill and VGPRSpill,
SGPRSpill is for global/constant memory related GPR registers spill, VGPRSpill
is for private/shared memory related VGPR registers spill
 2023-06-07 11:57:20 +08:00
zhoujing 033505de1d [VENTUS][RISCV][fix] Modify calling convention 2023-06-05 17:11:25 +08:00
zhoujing 967cb725c8 [VENTUS][RISCV][feat] Set ventus kernel for OpenCL kernel functions 2023-06-05 13:10:35 +08:00
zhoujing 8e86eb368c [VENTUS][RISCV][workflow] Modify workflow script 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:03:02 +08:00
zhoujing 7d66e05b28 [VENTUS][RISCV][fix] Fix insert join instructions pass bug 
After this fix, the vbeq/join instructions codegen are normal now

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:02:27 +08:00
zhoujing 8c7f5a3c28 [VENTUS][RISCV][fix] Fix instructuions which contain 5 bits unsigned immediate asmParser && pattern bug 2023-05-26 17:52:36 +08:00
zhoujing b22d7bd36f [VENTUS][RISCV][fix] Fix vlw/vsw instructions' pattern 2023-05-26 11:12:48 +08:00
zhoujing a17f01270b [VENTUS][RISCV][fix] Fix vlw12.v/vsw12.v instructions' codegen pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:49:48 +08:00
zhoujingya ad23baaa51 [VENTUS][RISCV][feat] Add more floating point instructions pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:48:30 +08:00
zhoujing 5d29133ab0 [VENTUS][RISCV][fix] Add isReturn block check before insertation 2023-05-25 14:09:12 +08:00
zhoujingya c0cdbbc172 [VENTUS][RISCV][style] Formatting && Change function and variable names 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-12 17:41:45 +08:00
zhoujingya 961d5a6b42 [VENTUS][RISCV][fix] Uncomment missing assertation 2023-05-12 14:46:27 +08:00
zhoujingya 97a3f99e4c [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch 
we follow the following rules to insert join block and join instruction

 1: Legalize all the return block
    when there are one more return blocks in machine function, there must be
    branches, we need to reduce return blocks number down to 1
 1.1: If two return blocks have common nearest parent branch, this two blocks
    need to be joined, and we add a hasBeenJoined marker for this parent
    branch
 1.2: after we complete 1.1 process, there maybe one more return blocks, we
    need to further add join block, we recursively build dominator tree for
    these return blocks, first we find the nearest common dominator branch for
    two return blocks, and then get dominator tree path between dominator
    and each return block, we need to check this path in which whether any
    other branch blocks exists, ideally, the branch block in path should have
    been joined and marked, if not, this path is illegal, these two block can
    not be joined

 2: Insert join instructions
 2.1: we scan through the MachineBasic blocks and check what blocks to insert
    join instruction, below MBB represents MachineBasic Block
 2.2: The MBB must have one more predecessors and its nearest dominator must
     be a VBranch
 2.3: Then we analyze the the predecessor of MBB, if the predecessor
    has single successor, we add a join instruction to the predecessor end,
    other wise, we need to insert a join block between predecessor and MBB
 2023-05-12 14:01:57 +08:00
zhoujingya 5f776bde21 [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
zhoujingya ea75d078fb [VENTUS][RISCV][feat] Add zfinx support 
Because there is no `F` extension and float registers in ventus, we need to
support `zfinx` to generate common float instructions
 2023-04-23 11:29:09 +08:00
zhoujingya 9d9283fa7b [VENTUS][RISCV][fix] Fix ventus abi and calling convention 
Kernel functions use sp as GPRs spill stack slots
Non-kernel functions use tp as VGPRs spill stack slots
 2023-04-20 15:27:52 +08:00