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[VENTUS][fix] Fix illegal bitcast

This commit is contained in:
zhoujingya 2023-09-19 17:51:48 +08:00 committed by zhoujingya
parent 4bfde6aa71
commit fb8e1be577
2 changed files with 9 additions and 10 deletions
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13
llvm/lib/Target/RISCV/VentusInstrInfo.td
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@ -1811,9 +1811,10 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
} // Predicates = [IsRV64], ...
/// Loads
multiclass UniformLdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {
def : Pat<(vt (UniformLoadFrag<LoadOp> (AddrRegImm GPRNoX4:$rs1, simm12:$imm12))),
(Inst GPR:$rs1, simm12:$imm12)>;
multiclass UniformLdPat<PatFrag LoadOp, RVInst Inst,
ValueType vt = XLenVT, RegisterClass StTy = GPR> {
def : Pat<(vt (UniformLoadFrag<LoadOp>
(AddrRegImm GPRNoX4:$rs1, simm12:$imm12))), (Inst StTy:$rs1, simm12:$imm12)>;
}
defm : UniformLdPat<sextloadi8, LB>;
@ -2007,10 +2008,8 @@ defm : UniformStPat<store, SD, GPR, i64>;
// FIXME: It is still work by omitting 2 of the following bitcast patterns.
let Predicates = [HasStdExtZfinx] in {
def : Pat<(i32 (bitconvert f32:$src)), (i32 GPR:$src)>;
def : Pat<(i32 (bitconvert f32:$src)), (i32 VGPR:$src)>;
def : Pat<(f32 (bitconvert i32:$src)), (f32 GPRF32:$src)>;
def : Pat<(f32 (bitconvert i32:$src)), (f32 VGPR:$src)>;
def : Pat<(i32 (DivergentUnaryFrag<bitconvert> (f32 GPRF32:$src))), (i32 VGPR:$src)>;
def : Pat<(f32 (DivergentUnaryFrag<bitconvert> i32:$src)), (f32 VGPR:$src)>;
} // Predicates = [HasStdExtZfinx]
/// readcyclecounter

6
llvm/lib/Target/RISCV/VentusInstrInfoF.td
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@ -450,8 +450,8 @@ defm : FPUnaryOpDynFrmAlias_m<FCVT_S_LU, "fcvt.s.lu", FXIN64X>;
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZfinx] in {
def : InstAlias<"flw $rd, (${rs1})", (FLW GPRF32:$rd, GPR:$rs1, 0), 0>;
def : InstAlias<"fsw $rs2, (${rs1})", (FSW GPRF32:$rs2, GPR:$rs1, 0), 0>;
def : InstAlias<"flw $rd, (${rs1})", (FLW GPRF32:$rd, GPRF32:$rs1, 0), 0>;
def : InstAlias<"fsw $rs2, (${rs1})", (FSW GPRF32:$rs2, GPRF32:$rs1, 0), 0>;
def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>;
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>;
@ -638,7 +638,7 @@ def PseudoFROUND_S : PseudoFROUND<GPRF32>;
/// Loads
defm : UniformLdPat<load, FLW, f32>;
defm : UniformLdPat<load, FLW, f32, GPRF32>;
/// Stores