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[AArch64] Regenerate andandshift.ll test checks

This commit is contained in:
Simon Pilgrim 2022-05-23 11:48:24 +01:00
parent 8717b492df
commit dd231f02a3
1 changed files with 14 additions and 6 deletions
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20
llvm/test/CodeGen/AArch64/andandshift.ll
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@ -1,11 +1,15 @@
; RUN: llc -O3 < %s | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "arm64--linux-gnu"
; Function Attrs: nounwind readnone
define i32 @test1(i8 %a) {
; CHECK-LABEL: @test1
; CHECK: ubfx {{w[0-9]+}}, w0, #3, #5
; CHECK-LABEL: test1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ubfx w0, w0, #3, #5
; CHECK-NEXT: ret
entry:
%conv = zext i8 %a to i32
%shr1 = lshr i32 %conv, 3
@ -14,9 +18,13 @@ entry:
; Function Attrs: nounwind readnone
define i32 @test2(i8 %a) {
; CHECK-LABEL: @test2
; CHECK: and {{w[0-9]+}}, w0, #0xff
; CHECK: ubfx {{w[0-9]+}}, w0, #3, #5
; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: ubfx w9, w0, #3, #5
; CHECK-NEXT: cmp w8, #47
; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
entry:
%conv = zext i8 %a to i32
%cmp = icmp ugt i8 %a, 47