forked from OSchip/llvm-project
[VENTUS][fix] Fix the Offset of private variable offset on stack
Fix the Offset of private variable offset on stack.
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755797e27c
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@ -81,7 +81,7 @@ __builtin_riscv_workitem_linear_id:
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.type __builtin_riscv_global_linear_id, @function
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__builtin_riscv_global_linear_id:
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addi sp, sp, 4
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sw ra, 0(sp)
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sw ra, -4(sp)
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csrr a3, CSR_KNL # Get kernel metadata buffer
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lw t0, KNL_WORK_DIM(a3) # Get work_dims
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call __builtin_riscv_global_id_x
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@ -109,7 +109,7 @@ __builtin_riscv_global_linear_id:
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vadd.vv v5, v5, v6 # global_linear_id3 = tmp + global_linear_id2
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.GLR:
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vadd.vx v0, v5, zero # Return global_linear_id for 1/2/3 dims
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lw ra, 0(sp)
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lw ra, -4(sp)
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addi sp, sp, -4
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ret
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@ -202,7 +202,7 @@ __builtin_riscv_workitem_id_z:
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.type __builtin_riscv_global_id_x, @function
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__builtin_riscv_global_id_x:
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addi sp, sp, 4
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sw ra, 0(sp)
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sw ra, -4(sp)
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call __builtin_riscv_workitem_id_x
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csrr a0, CSR_KNL # Get kernel metadata buffer
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csrr t1, CSR_GID_X # Get group_id_x
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@ -211,7 +211,7 @@ __builtin_riscv_global_id_x:
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mul t6, t1, t3 # CSR_GID_X * local_size_x
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add t6, t6, t4 # Get global_offset_x + CSR_GID_X * local_size_x
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vadd.vx v0,v0, t6
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lw ra, 0(sp)
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lw ra, -4(sp)
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addi sp, sp, -4
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ret
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@ -221,7 +221,7 @@ __builtin_riscv_global_id_x:
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.type __builtin_riscv_global_id_y, @function
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__builtin_riscv_global_id_y:
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addi sp, sp, 4
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sw ra, 0(sp)
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sw ra, -4(sp)
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call __builtin_riscv_workitem_id_y
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csrr t1, CSR_GID_Y # Get group_id_y
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lw t2, KNL_LC_SIZE_Y(a0) # Get local_size_y
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@ -229,7 +229,7 @@ __builtin_riscv_global_id_y:
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mul t3, t1, t2 # CSR_GID_Y * local_size_y
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add t3, t3, t4 # global_offset_y + (CSR_GID_Y * local_size_y)
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vadd.vx v0, v0, t3 # global_id_y
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lw ra, 0(sp)
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lw ra, -4(sp)
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addi sp, sp, -4
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ret
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@ -239,7 +239,7 @@ __builtin_riscv_global_id_y:
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.type __builtin_riscv_global_id_z, @function
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__builtin_riscv_global_id_z:
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addi sp, sp, 4
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sw ra, 0(sp)
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sw ra, -4(sp)
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call __builtin_riscv_workitem_id_z
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csrr a0, CSR_KNL # Get kernel metadata buffer
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csrr t1, CSR_GID_Z # Get group_id_z
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@ -248,7 +248,7 @@ __builtin_riscv_global_id_z:
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mul t2, t2, t1 # CSR_GID_Z * local_size_z
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add t2, t2, t3 # global_offset_z + (CSR_GID_Z * local_size_z)
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vadd.vx v0, v0, t2 # global_id_z
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lw ra, 0(sp)
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lw ra, -4(sp)
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addi sp, sp, -4
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ret
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@ -387,4 +387,3 @@ __builtin_riscv_work_dim:
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lw t0, KNL_WORK_DIM(a0) # Get work_dim
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vmv.v.x v0, t0
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ret
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@ -521,13 +521,13 @@ uint64_t RISCVFrameLowering::getStackOffset(const MachineFunction &MF,
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// because the parameters spilling to the stack are not in the current TP
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// stack, the offset in the current stack should not be calculated from a
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// negative FI.
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for (int I = FI < 0 ? MFI.getObjectIndexBegin() : 0; I != FI; I++) {
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for (int I = FI < 0 ? MFI.getObjectIndexBegin() : 0; I != FI + 1; I++) {
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if (static_cast<unsigned>(MFI.getStackID(I)) == Stack) {
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// Need to consider the alignment for different frame index
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Align Alignment =
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MFI.getObjectAlign(I).value() <= 4 ? Align(4) : MFI.getObjectAlign(I);
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uint64_t AlignedSize = alignTo(MFI.getObjectSize(I), Alignment);
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StackSize += AlignedSize;
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StackSize += MFI.getObjectSize(I);
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StackSize = alignTo(StackSize, Alignment);
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}
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}
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@ -537,7 +537,7 @@ uint64_t RISCVFrameLowering::getStackOffset(const MachineFunction &MF,
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if (FI < 0 && !MF.getFunction().isVarArg())
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StackSize += getStackSize(MF, RISCVStackID::VGPRSpill);
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return alignTo(StackSize, Align(4));
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return StackSize;
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}
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StackOffset
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@ -11832,7 +11832,6 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
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else
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analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false, CC_Ventus);
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SmallVector<SDValue> MemVec;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue ArgValue;
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@ -11859,15 +11858,8 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
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ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
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else if (VA.isRegLoc())
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ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL, *this, Ins[i]);
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else {
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// Temporarily put the created parameter node to MemVec instead of to
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// InVals directly because it will be reversed later and then put to
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// InVals.
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else
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ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
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MemVec.push_back(ArgValue);
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continue;
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}
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if (VA.getLocInfo() == CCValAssign::Indirect) {
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// If the original argument was split and passed by reference (e.g. i128
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@ -11897,12 +11889,6 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
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}
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}
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// Reverse MemVec and fill in InVals to ensure that the order in which the
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// callee functions are fetched is the same as the order in which it was
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// processed here.
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while (MemVec.size())
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InVals.push_back(MemVec.pop_back_val());
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if (IsVarArg) {
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// When it come to vardic arguments, the vardic function also need to follow
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// no-kernel function calling convention, we need to use VGPRs to pass
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@ -12124,6 +12110,9 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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SDValue StackPtr;
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// Get the value of adjusting the stack frame before the Call.
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uint64_t CurrentFrameSize = Chain->getConstantOperandVal(1);
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for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue ArgValue = OutVals[i];
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@ -12229,8 +12218,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X4, PtrVT);
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SDValue Address =
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DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
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DAG.getIntPtrConstant((int)VA.getLocMemOffset() > 0 ?
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(-VA.getLocMemOffset()) : VA.getLocMemOffset(), DL));
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DAG.getIntPtrConstant(-((int)VA.getLocMemOffset()
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+ CurrentFrameSize), DL));
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// Emit the store.
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MemOpChains.push_back(
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