forked from OSchip/llvm-project
[X86] Remove little support we had for MPX
GCC 9.1 removed Intel MPX support. Linux kernel removed MPX in 2019. glibc 2.35 will remove MPX. Our support is limited: we support assembling of bndmov but not bnd. Just remove it. Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D111517
This commit is contained in:
Fangrui Song
parent
1b81581fee
commit
c2d4fe51bb
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@ -675,17 +675,6 @@ void t46() {
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// CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
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}
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void t47() {
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// CHECK-LABEL: define{{.*}} void @t47
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__asm {
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bndmk bnd0, dword ptr [eax]
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bndmk bnd1, dword ptr [ebx]
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bndmk bnd2, dword ptr [ecx]
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bndmk bnd3, dword ptr [edx]
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}
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// CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr [eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr [ecx]\0A\09bndmk bnd3, dword ptr [edx]", "~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"()
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}
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void dot_operator(){
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// CHECK-LABEL: define{{.*}} void @dot_operator
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__asm { mov eax, 3[ebx]A.b}
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@ -806,10 +806,6 @@ static int readModRM(struct InternalInstruction *insn) {
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return prefix##_DR0 + index; \
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case TYPE_CONTROLREG: \
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return prefix##_CR0 + index; \
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case TYPE_BNDR: \
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if (index > 3) \
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*valid = 0; \
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return prefix##_BND0 + index; \
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case TYPE_MVSIBX: \
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return prefix##_XMM0 + index; \
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case TYPE_MVSIBY: \
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@ -374,12 +374,6 @@ namespace X86Disassembler {
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ENTRY(CR14) \
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ENTRY(CR15)
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#define REGS_BOUND \
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ENTRY(BND0) \
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ENTRY(BND1) \
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ENTRY(BND2) \
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ENTRY(BND3)
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#undef REGS_TMM
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#define REGS_TMM \
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ENTRY(TMM0) \
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@ -414,7 +408,6 @@ namespace X86Disassembler {
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REGS_SEGMENT \
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REGS_DEBUG \
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REGS_CONTROL \
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REGS_BOUND \
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REGS_TMM \
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ENTRY(RIP)
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@ -3718,12 +3718,6 @@ static unsigned getLoadStoreRegOpcode(Register Reg,
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HasAVX ? X86::VMOVUPSmr :
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X86::MOVUPSmr);
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}
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if (X86::BNDRRegClass.hasSubClassEq(RC)) {
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if (STI.is64Bit())
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return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
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else
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return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
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}
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llvm_unreachable("Unknown 16-byte regclass");
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}
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case 32:
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@ -3159,9 +3159,6 @@ include "X86InstrAVX512.td"
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include "X86InstrMMX.td"
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include "X86Instr3DNow.td"
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// MPX instructions
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include "X86InstrMPX.td"
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include "X86InstrVMX.td"
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include "X86InstrSVM.td"
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include "X86InstrSNP.td"
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@ -1,77 +0,0 @@
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//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MPX instruction set, defining the
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// instructions, and properties of the instructions which are needed for code
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// generation, machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM.
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let SchedRW = [WriteSystem] in {
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multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
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def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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Requires<[Not64BitMode]>;
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def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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Requires<[In64BitMode]>;
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}
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defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
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multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
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def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[Not64BitMode]>;
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def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[In64BitMode]>;
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def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[Not64BitMode]>;
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def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[In64BitMode]>;
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}
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defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable;
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defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable;
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defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable;
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def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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NotMemoryFoldable;
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let mayLoad = 1 in {
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def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[Not64BitMode]>, NotMemoryFoldable;
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def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[In64BitMode]>, NotMemoryFoldable;
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}
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let isCodeGenOnly = 1, ForceDisassemble = 1 in
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def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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NotMemoryFoldable;
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let mayStore = 1 in {
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def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[Not64BitMode]>, NotMemoryFoldable;
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def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[In64BitMode]>, NotMemoryFoldable;
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def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src),
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"bndstx\t{$src, $dst|$dst, $src}", []>, PS;
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}
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let mayLoad = 1 in
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def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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"bndldx\t{$src, $dst|$dst, $src}", []>, PS;
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} // SchedRW
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@ -373,12 +373,6 @@ def CR15 : X86Reg<"cr15", 15>;
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def EIZ : X86Reg<"eiz", 4>;
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def RIZ : X86Reg<"riz", 4>;
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// Bound registers, used in MPX instructions
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def BND0 : X86Reg<"bnd0", 0>;
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def BND1 : X86Reg<"bnd1", 1>;
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def BND2 : X86Reg<"bnd2", 2>;
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def BND3 : X86Reg<"bnd3", 3>;
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// CET registers - Shadow Stack Pointer
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def SSP : X86Reg<"ssp", 0>;
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@ -640,9 +634,6 @@ def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
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def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
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def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
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// Bound registers
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def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;
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// Tiles
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let CopyCost = -1 in // Don't allow copying of tile registers
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def TILE : RegisterClass<"X86", [x86amx], 8192,
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@ -3,7 +3,7 @@
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target triple = "x86_64-unknown-unknown"
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declare void @bar1()
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define preserve_allcc void @foo()#0 {
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; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7
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; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7
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call void @bar1()
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call void @bar2()
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ret void
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@ -1,41 +0,0 @@
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// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\
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// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING
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// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\
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// RUN: llvm-objdump -d - | FileCheck %s
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// CHECK: bndmk (%rax), %bnd0
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// ENCODING: encoding: [0xf3,0x0f,0x1b,0x00]
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bndmk (%rax), %bnd0
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// CHECK: bndmk 1024(%rax), %bnd1
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// ENCODING: encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
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bndmk 1024(%rax), %bnd1
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// CHECK: bndmov %bnd2, %bnd1
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// ENCODING: encoding: [0x66,0x0f,0x1a,0xca]
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bndmov %bnd2, %bnd1
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// CHECK: bndmov %bnd1, 1024(%r9)
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// ENCODING: encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
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bndmov %bnd1, 1024(%r9)
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// CHECK: bndstx %bnd1, 1024(%rax)
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// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
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bndstx %bnd1, 1024(%rax)
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// CHECK: bndldx 1024(%r8), %bnd1
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// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
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bndldx 1024(%r8), %bnd1
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// CHECK: bndcl 121(%r10), %bnd1
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// ENCODING: encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79]
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bndcl 121(%r10), %bnd1
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// CHECK: bndcn 121(%rcx), %bnd3
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// ENCODING: encoding: [0xf2,0x0f,0x1b,0x59,0x79]
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bndcn 121(%rcx), %bnd3
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// CHECK: bndcu %rdx, %bnd3
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// ENCODING: encoding: [0xf2,0x0f,0x1a,0xda]
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bndcu %rdx, %bnd3
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@ -213,26 +213,6 @@ TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
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ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
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}
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TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) {
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// - BNDCL32rr
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// - Op0 Explicit Use RegClass(BNDR)
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// - Op1 Explicit Use RegClass(GR32)
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// - Var0 [Op0]
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// - Var1 [Op1]
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const unsigned Opcode = X86::BNDCL32rr;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info, HasSubstr("parallel"));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
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EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
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EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
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}
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TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) {
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// - CDQ
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// - Op0 Implicit Def Reg(EAX)
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