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CodeGen/CommandFlags: Convert Optional to std::optional

This commit is contained in:
Fangrui Song 2022-12-03 18:38:12 +00:00
parent d7a1351bb8
commit bac974278c
65 changed files with 126 additions and 138 deletions
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2
lld/Common/TargetOptionsCommandFlags.cpp
View File

@ -16,7 +16,7 @@ llvm::TargetOptions lld::initTargetOptionsFromCodeGenFlags() {
return llvm::codegen::InitTargetOptionsFromCodeGenFlags(llvm::Triple());
}
llvm::Optional<llvm::Reloc::Model> lld::getRelocModelFromCMModel() {
std::optional<llvm::Reloc::Model> lld::getRelocModelFromCMModel() {
return llvm::codegen::getExplicitRelocModel();
}

3
lld/include/lld/Common/TargetOptionsCommandFlags.h
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@ -13,14 +13,13 @@
#ifndef LLD_COMMON_TARGETOPTIONSCOMMANDFLAGS_H
#define LLD_COMMON_TARGETOPTIONSCOMMANDFLAGS_H
#include "llvm/ADT/Optional.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetOptions.h"
#include <optional>
namespace lld {
llvm::TargetOptions initTargetOptionsFromCodeGenFlags();
llvm::Optional<llvm::Reloc::Model> getRelocModelFromCMModel();
std::optional<llvm::Reloc::Model> getRelocModelFromCMModel();
std::optional<llvm::CodeModel::Model> getCodeModelFromCMModel();
std::string getCPUStr();
std::vector<std::string> getMAttrs();

8
llvm/include/llvm/CodeGen/CommandFlags.h
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@ -38,7 +38,7 @@ std::string getMCPU();
std::vector<std::string> getMAttrs();
Reloc::Model getRelocModel();
Optional<Reloc::Model> getExplicitRelocModel();
std::optional<Reloc::Model> getExplicitRelocModel();
ThreadModel::Model getThreadModel();
@ -47,7 +47,7 @@ std::optional<CodeModel::Model> getExplicitCodeModel();
llvm::ExceptionHandling getExceptionModel();
Optional<CodeGenFileType> getExplicitFileType();
std::optional<CodeGenFileType> getExplicitFileType();
CodeGenFileType getFileType();
@ -99,10 +99,10 @@ bool getLowerGlobalDtorsViaCxaAtExit();
bool getRelaxELFRelocations();
bool getDataSections();
Optional<bool> getExplicitDataSections();
std::optional<bool> getExplicitDataSections();
bool getFunctionSections();
Optional<bool> getExplicitFunctionSections();
std::optional<bool> getExplicitFunctionSections();
bool getIgnoreXCOFFVisibility();

2
llvm/include/llvm/ExecutionEngine/ExecutionEngine.h
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@ -541,7 +541,7 @@ private:
std::shared_ptr<MCJITMemoryManager> MemMgr;
std::shared_ptr<LegacyJITSymbolResolver> Resolver;
TargetOptions Options;
Optional<Reloc::Model> RelocModel;
std::optional<Reloc::Model> RelocModel;
std::optional<CodeModel::Model> CMModel;
std::string MArch;
std::string MCPU;

6
llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
View File

@ -84,13 +84,13 @@ public:
const std::string &getCPU() const { return CPU; }
/// Set the relocation model.
JITTargetMachineBuilder &setRelocationModel(Optional<Reloc::Model> RM) {
JITTargetMachineBuilder &setRelocationModel(std::optional<Reloc::Model> RM) {
this->RM = std::move(RM);
return *this;
}
/// Get the relocation model.
const Optional<Reloc::Model> &getRelocationModel() const { return RM; }
const std::optional<Reloc::Model> &getRelocationModel() const { return RM; }
/// Set the code model.
JITTargetMachineBuilder &setCodeModel(std::optional<CodeModel::Model> CM) {
@ -151,7 +151,7 @@ private:
std::string CPU;
SubtargetFeatures Features;
TargetOptions Options;
Optional<Reloc::Model> RM;
std::optional<Reloc::Model> RM;
std::optional<CodeModel::Model> CM;
CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
};

2
llvm/include/llvm/LTO/Config.h
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@ -52,7 +52,7 @@ struct Config {
std::vector<std::string> PassPlugins;
/// For adding passes that run right before codegen.
std::function<void(legacy::PassManager &)> PreCodeGenPassesHook;
Optional<Reloc::Model> RelocModel = Reloc::PIC_;
std::optional<Reloc::Model> RelocModel = Reloc::PIC_;
std::optional<CodeModel::Model> CodeModel = std::nullopt;
CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default;
CodeGenFileType CGFileType = CGFT_ObjectFile;

2
llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
View File

@ -89,7 +89,7 @@ struct LTOCodeGenerator {
void setAsmUndefinedRefs(struct LTOModule *);
void setTargetOptions(const TargetOptions &Options);
void setDebugInfo(lto_debug_model);
void setCodePICModel(Optional<Reloc::Model> Model) {
void setCodePICModel(std::optional<Reloc::Model> Model) {
Config.RelocModel = Model;
}

4
llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
View File

@ -37,7 +37,7 @@ struct TargetMachineBuilder {
std::string MCpu;
std::string MAttr;
TargetOptions Options;
Optional<Reloc::Model> RelocModel;
std::optional<Reloc::Model> RelocModel;
CodeGenOpt::Level CGOptLevel = CodeGenOpt::Aggressive;
std::unique_ptr<TargetMachine> create() const;
@ -211,7 +211,7 @@ public:
void setFreestanding(bool Enabled) { Freestanding = Enabled; }
/// CodeModel
void setCodePICModel(Optional<Reloc::Model> Model) {
void setCodePICModel(std::optional<Reloc::Model> Model) {
TMBuilder.RelocModel = Model;
}

15
llvm/include/llvm/MC/TargetRegistry.h
View File

@ -167,7 +167,7 @@ public:
StringRef Features);
using TargetMachineCtorTy = TargetMachine
*(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, Optional<Reloc::Model> RM,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
// If it weren't for layering issues (this header is in llvm/Support, but
// depends on MC?) this should take the Streamer by value rather than rvalue
@ -479,12 +479,11 @@ public:
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
TargetMachine *
createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, Optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM = std::nullopt,
CodeGenOpt::Level OL = CodeGenOpt::Default,
bool JIT = false) const {
TargetMachine *createTargetMachine(
StringRef TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM = std::nullopt,
CodeGenOpt::Level OL = CodeGenOpt::Default, bool JIT = false) const {
if (!TargetMachineCtorFn)
return nullptr;
return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
@ -1362,7 +1361,7 @@ private:
static TargetMachine *Allocator(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT) {
return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);

14
llvm/lib/CodeGen/CommandFlags.cpp
View File

@ -41,18 +41,8 @@ using namespace llvm;
return *NAME##View; \
}
#define CGOPT_EXP(TY, NAME) \
CGOPT(TY, NAME) \
Optional<TY> codegen::getExplicit##NAME() { \
if (NAME##View->getNumOccurrences()) { \
TY res = *NAME##View; \
return res; \
} \
return None; \
}
// Temporary macro for incremental transition to std::optional.
#define CGSTDOPT_EXP(TY, NAME) \
#define CGOPT_EXP(TY, NAME) \
CGOPT(TY, NAME) \
std::optional<TY> codegen::getExplicit##NAME() { \
if (NAME##View->getNumOccurrences()) { \
@ -67,7 +57,7 @@ CGOPT(std::string, MCPU)
CGLIST(std::string, MAttrs)
CGOPT_EXP(Reloc::Model, RelocModel)
CGOPT(ThreadModel::Model, ThreadModel)
CGSTDOPT_EXP(CodeModel::Model, CodeModel)
CGOPT_EXP(CodeModel::Model, CodeModel)
CGOPT(ExceptionHandling, ExceptionModel)
CGOPT_EXP(CodeGenFileType, FileType)
CGOPT(FramePointerKind, FramePointerUsage)

2
llvm/lib/LTO/LTOBackend.cpp
View File

@ -208,7 +208,7 @@ createTargetMachine(const Config &Conf, const Target *TheTarget, Module &M) {
for (const std::string &A : Conf.MAttrs)
Features.AddFeature(A);
Optional<Reloc::Model> RelocModel;
std::optional<Reloc::Model> RelocModel;
if (Conf.RelocModel)
RelocModel = *Conf.RelocModel;
else if (M.getModuleFlag("PIC Level"))

8
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -275,7 +275,7 @@ static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
// AArch64 Darwin and Windows are always PIC.
if (TT.isOSDarwin() || TT.isOSWindows())
return Reloc::PIC_;
@ -315,7 +315,7 @@ getEffectiveAArch64CodeModel(const Triple &TT,
AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT,
bool LittleEndian)
@ -454,7 +454,7 @@ void AArch64leTargetMachine::anchor() { }
AArch64leTargetMachine::AArch64leTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
@ -462,7 +462,7 @@ void AArch64beTargetMachine::anchor() { }
AArch64beTargetMachine::AArch64beTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}

6
llvm/lib/Target/AArch64/AArch64TargetMachine.h
View File

@ -29,7 +29,7 @@ protected:
public:
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT, bool IsLittleEndian);
@ -75,7 +75,7 @@ class AArch64leTargetMachine : public AArch64TargetMachine {
public:
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
@ -88,7 +88,7 @@ class AArch64beTargetMachine : public AArch64TargetMachine {
public:
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};

6
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -522,7 +522,7 @@ static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
return "r600";
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
// The AMDGPU toolchain only supports generating shared objects, so we
// must always use PIC.
return Reloc::PIC_;
@ -531,7 +531,7 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
@ -801,7 +801,7 @@ AMDGPUTargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}

4
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
View File

@ -40,7 +40,7 @@ public:
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine() override;
@ -78,7 +78,7 @@ private:
public:
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

2
llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
View File

@ -51,7 +51,7 @@ static MachineSchedRegistry R600SchedRegistry("r600",
R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {

2
llvm/lib/Target/AMDGPU/R600TargetMachine.h
View File

@ -32,7 +32,7 @@ private:
public:
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

4
llvm/lib/Target/ARC/ARCTargetMachine.cpp
View File

@ -21,7 +21,7 @@
using namespace llvm;
static Reloc::Model getRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
@ -29,7 +29,7 @@ static Reloc::Model getRelocModel(Optional<Reloc::Model> RM) {
ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T,

2
llvm/lib/Target/ARC/ARCTargetMachine.h
View File

@ -28,7 +28,7 @@ class ARCTargetMachine : public LLVMTargetMachine {
public:
ARCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~ARCTargetMachine() override;

8
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -196,7 +196,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
if (!RM)
// Default relocation model on Darwin is PIC.
return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
@ -217,7 +217,7 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
@ -317,7 +317,7 @@ ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
@ -325,7 +325,7 @@ ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}

6
llvm/lib/Target/ARM/ARMTargetMachine.h
View File

@ -42,7 +42,7 @@ protected:
public:
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool isLittle);
~ARMBaseTargetMachine() override;
@ -88,7 +88,7 @@ class ARMLETargetMachine : public ARMBaseTargetMachine {
public:
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
@ -99,7 +99,7 @@ class ARMBETargetMachine : public ARMBaseTargetMachine {
public:
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};

4
llvm/lib/Target/AVR/AVRTargetMachine.cpp
View File

@ -39,14 +39,14 @@ static StringRef getCPU(StringRef CPU) {
return CPU;
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,

2
llvm/lib/Target/AVR/AVRTargetMachine.h
View File

@ -31,7 +31,7 @@ class AVRTargetMachine : public LLVMTargetMachine {
public:
AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

4
llvm/lib/Target/BPF/BPFTargetMachine.cpp
View File

@ -58,14 +58,14 @@ static std::string computeDataLayout(const Triple &TT) {
return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::PIC_);
}
BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,

2
llvm/lib/Target/BPF/BPFTargetMachine.h
View File

@ -25,7 +25,7 @@ class BPFTargetMachine : public LLVMTargetMachine {
public:
BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

2
llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
View File

@ -49,7 +49,7 @@ static std::string computeDataLayout(const Triple &TT) {
CSKYTargetMachine::CSKYTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,

2
llvm/lib/Target/CSKY/CSKYTargetMachine.h
View File

@ -27,7 +27,7 @@ class CSKYTargetMachine : public LLVMTargetMachine {
public:
CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

2
llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
View File

@ -83,7 +83,7 @@ public:
DirectXTargetMachine::DirectXTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T,

2
llvm/lib/Target/DirectX/DirectXTargetMachine.h
View File

@ -24,7 +24,7 @@ class DirectXTargetMachine : public LLVMTargetMachine {
public:
DirectXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

4
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -193,7 +193,7 @@ namespace llvm {
FunctionPass *createHexagonVExtract();
} // end namespace llvm;
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
@ -223,7 +223,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
// Specify the vector alignment explicitly. For v512x1, the calculated

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.h
View File

@ -30,7 +30,7 @@ class HexagonTargetMachine : public LLVMTargetMachine {
public:
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~HexagonTargetMachine() override;

4
llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
View File

@ -48,13 +48,13 @@ static std::string computeDataLayout() {
"-S64"; // 64 bit natural stack alignment
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::PIC_);
}
LanaiTargetMachine::LanaiTargetMachine(
const Target &T, const Triple &TT, StringRef Cpu, StringRef FeatureString,
const TargetOptions &Options, Optional<Reloc::Model> RM,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CodeModel, CodeGenOpt::Level OptLevel,
bool JIT)
: LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,

2
llvm/lib/Target/Lanai/LanaiTargetMachine.h
View File

@ -30,7 +30,7 @@ public:
LanaiTargetMachine(const Target &TheTarget, const Triple &TargetTriple,
StringRef Cpu, StringRef FeatureString,
const TargetOptions &Options,
Optional<Reloc::Model> RelocationModel,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CodeModel,
CodeGenOpt::Level OptLevel, bool JIT);

4
llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
View File

@ -40,13 +40,13 @@ static std::string computeDataLayout(const Triple &TT) {
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
LoongArchTargetMachine::LoongArchTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),

2
llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
View File

@ -26,7 +26,7 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
public:
LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~LoongArchTargetMachine() override;

4
llvm/lib/Target/M68k/M68kTargetMachine.cpp
View File

@ -71,7 +71,7 @@ std::string computeDataLayout(const Triple &TT, StringRef CPU,
}
Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
// If not defined we default to static
if (!RM.has_value())
return Reloc::Static;
@ -95,7 +95,7 @@ CodeModel::Model getEffectiveCodeModel(std::optional<CodeModel::Model> CM,
M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,

2
llvm/lib/Target/M68k/M68kTargetMachine.h
View File

@ -37,7 +37,7 @@ class M68kTargetMachine : public LLVMTargetMachine {
public:
M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

4
llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -27,7 +27,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() {
RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target());
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
@ -39,7 +39,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,

2
llvm/lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -30,7 +30,7 @@ class MSP430TargetMachine : public LLVMTargetMachine {
public:
MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~MSP430TargetMachine() override;

8
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -106,7 +106,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
}
static Reloc::Model getEffectiveRelocModel(bool JIT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
if (!RM || JIT)
return Reloc::Static;
return *RM;
@ -120,7 +120,7 @@ static Reloc::Model getEffectiveRelocModel(bool JIT,
MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT,
bool isLittle)
@ -149,7 +149,7 @@ void MipsebTargetMachine::anchor() {}
MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
@ -159,7 +159,7 @@ void MipselTargetMachine::anchor() {}
MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}

6
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@ -40,7 +40,7 @@ class MipsTargetMachine : public LLVMTargetMachine {
public:
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT, bool isLittle);
~MipsTargetMachine() override;
@ -85,7 +85,7 @@ class MipsebTargetMachine : public MipsTargetMachine {
public:
MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
@ -98,7 +98,7 @@ class MipselTargetMachine : public MipsTargetMachine {
public:
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};

6
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -112,7 +112,7 @@ static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool is64bit)
// The pic relocation model is used regardless of what the client has
@ -139,7 +139,7 @@ void NVPTXTargetMachine32::anchor() {}
NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
@ -149,7 +149,7 @@ void NVPTXTargetMachine64::anchor() {}
NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}

6
llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@ -37,7 +37,7 @@ class NVPTXTargetMachine : public LLVMTargetMachine {
public:
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OP,
bool is64bit);
~NVPTXTargetMachine() override;
@ -81,7 +81,7 @@ class NVPTXTargetMachine32 : public NVPTXTargetMachine {
public:
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
@ -92,7 +92,7 @@ class NVPTXTargetMachine64 : public NVPTXTargetMachine {
public:
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};

4
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -246,7 +246,7 @@ static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
assert((!TT.isOSAIX() || !RM || *RM == Reloc::PIC_) &&
"Invalid relocation model for AIX.");
@ -325,7 +325,7 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler(
PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,

2
llvm/lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -38,7 +38,7 @@ private:
public:
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

4
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View File

@ -76,14 +76,14 @@ static StringRef computeDataLayout(const Triple &TT) {
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,

2
llvm/lib/Target/RISCV/RISCVTargetMachine.h
View File

@ -28,7 +28,7 @@ class RISCVTargetMachine : public LLVMTargetMachine {
public:
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

4
llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
View File

@ -53,7 +53,7 @@ static std::string computeDataLayout(const Triple &TT) {
"v96:128-v192:256-v256:256-v512:512-v1024:1024";
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
if (!RM)
return Reloc::PIC_;
return *RM;
@ -65,7 +65,7 @@ SPIRVTargetObjectFile::~SPIRVTargetObjectFile() {}
SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,

2
llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
View File

@ -25,7 +25,7 @@ class SPIRVTargetMachine : public LLVMTargetMachine {
public:
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);

10
llvm/lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -55,7 +55,7 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) {
return Ret;
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
@ -91,7 +91,7 @@ getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM,
SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT,
bool is64bit)
@ -191,7 +191,7 @@ void SparcV8TargetMachine::anchor() { }
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
@ -201,7 +201,7 @@ void SparcV9TargetMachine::anchor() { }
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
@ -211,7 +211,7 @@ void SparcelTargetMachine::anchor() {}
SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}

8
llvm/lib/Target/Sparc/SparcTargetMachine.h
View File

@ -29,7 +29,7 @@ class SparcTargetMachine : public LLVMTargetMachine {
public:
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT, bool is64bit);
~SparcTargetMachine() override;
@ -52,7 +52,7 @@ class SparcV8TargetMachine : public SparcTargetMachine {
public:
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
@ -65,7 +65,7 @@ class SparcV9TargetMachine : public SparcTargetMachine {
public:
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
@ -76,7 +76,7 @@ class SparcelTargetMachine : public SparcTargetMachine {
public:
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};

4
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -85,7 +85,7 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
return std::make_unique<TargetLoweringObjectFileELF>();
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
// Static code is suitable for use in a dynamic executable; there is no
// separate DynamicNoPIC model.
if (!RM || *RM == Reloc::DynamicNoPIC)
@ -140,7 +140,7 @@ getEffectiveSystemZCodeModel(std::optional<CodeModel::Model> CM,
SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(

2
llvm/lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -33,7 +33,7 @@ class SystemZTargetMachine : public LLVMTargetMachine {
public:
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~SystemZTargetMachine() override;

2
llvm/lib/Target/TargetMachineC.cpp
View File

@ -100,7 +100,7 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
const char *Triple, const char *CPU, const char *Features,
LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc,
LLVMCodeModel CodeModel) {
Optional<Reloc::Model> RM;
std::optional<Reloc::Model> RM;
switch (Reloc){
case LLVMRelocStatic:
RM = Reloc::Static;

4
llvm/lib/Target/VE/VETargetMachine.cpp
View File

@ -61,7 +61,7 @@ static std::string computeDataLayout(const Triple &T) {
return Ret;
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
@ -80,7 +80,7 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF() {
VETargetMachine::VETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,

5
llvm/lib/Target/VE/VETargetMachine.h
View File

@ -30,8 +30,9 @@ class VETargetMachine : public LLVMTargetMachine {
public:
VETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~VETargetMachine() override;
const VESubtarget *getSubtargetImpl() const { return &Subtarget; }

4
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
View File

@ -86,7 +86,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() {
// WebAssembly Lowering public interface.
//===----------------------------------------------------------------------===//
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM,
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM,
const Triple &TT) {
if (!RM) {
// Default to static relocation model. This should always be more optimial
@ -109,7 +109,7 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM,
///
WebAssemblyTargetMachine::WebAssemblyTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(
T,

2
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
View File

@ -28,7 +28,7 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
public:
WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);

7
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -163,9 +163,8 @@ static std::string computeDataLayout(const Triple &TT) {
return Ret;
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
bool JIT,
Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
std::optional<Reloc::Model> RM) {
bool is64Bit = TT.getArch() == Triple::x86_64;
if (!RM) {
// JIT codegen should use static relocations by default, since it's
@ -223,7 +222,7 @@ getEffectiveX86CodeModel(std::optional<CodeModel::Model> CM, bool JIT,
X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(

2
llvm/lib/Target/X86/X86TargetMachine.h
View File

@ -35,7 +35,7 @@ class X86TargetMachine final : public LLVMTargetMachine {
public:
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~X86TargetMachine() override;

4
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -26,7 +26,7 @@
using namespace llvm;
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
return RM.value_or(Reloc::Static);
}
@ -45,7 +45,7 @@ getEffectiveXCoreCodeModel(std::optional<CodeModel::Model> CM) {
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(

2
llvm/lib/Target/XCore/XCoreTargetMachine.h
View File

@ -31,7 +31,7 @@ class XCoreTargetMachine : public LLVMTargetMachine {
public:
XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
~XCoreTargetMachine() override;

2
llvm/tools/gold/gold-plugin.cpp
View File

@ -121,7 +121,7 @@ static ld_plugin_set_extra_library_path set_extra_library_path = nullptr;
static ld_plugin_get_view get_view = nullptr;
static bool IsExecutable = false;
static bool SplitSections = true;
static Optional<Reloc::Model> RelocationModel = None;
static std::optional<Reloc::Model> RelocationModel = None;
static std::string output_name = "";
static std::list<claimed_file> Modules;
static DenseMap<int, void *> FDToLeaderHandle;

2
llvm/tools/llc/llc.cpp
View File

@ -520,7 +520,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
}
};
Optional<Reloc::Model> RM = codegen::getExplicitRelocModel();
std::optional<Reloc::Model> RM = codegen::getExplicitRelocModel();
std::optional<CodeModel::Model> CM = codegen::getExplicitCodeModel();
const Target *TheTarget = nullptr;

2
llvm/tools/llvm-reduce/ReducerWorkItem.cpp
View File

@ -426,7 +426,7 @@ parseReducerWorkItem(const char *ToolName, StringRef Filename,
// Hopefully the MIR parsing doesn't depend on any options.
TargetOptions Options;
Optional<Reloc::Model> RM = codegen::getExplicitRelocModel();
std::optional<Reloc::Model> RM = codegen::getExplicitRelocModel();
std::string CPUStr = codegen::getCPUStr();
std::string FeaturesStr = codegen::getFeaturesStr();
TM = std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(