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[AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors in R600. 

This is a follow-on to https://reviews.llvm.org/D134073.

It renames a couple of fields to match their operands, as well as
introducing sub-operand names where required.

This change _only_ fixes the 'R600' half of the target, not the
'AMDGPU' half. Fixing the AMDGPU half will be a significantly more
difficult change (which I've not yet attempted.)

Differential Revision: https://reviews.llvm.org/D134078
This commit is contained in:
James Y Knight 2022-09-16 17:21:06 -04:00
parent 0f99958e79
commit a8c59bcc01
2 changed files with 7 additions and 9 deletions
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2
llvm/lib/Target/AMDGPU/R600.td
View File

@ -10,8 +10,6 @@ include "llvm/Target/Target.td"
def R600InstrInfo : InstrInfo {
let guessInstructionProperties = 1;
let noNamedPositionallyEncodedOperands = 1;
let useDeprecatedPositionallyEncodedOperands = 1;
}
def R600 : Target {

14
llvm/lib/Target/AMDGPU/R600Instructions.td
View File

@ -641,16 +641,16 @@ def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;
def FETCH_CLAUSE : R600WrapperInst <(outs),
(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
field bits<8> Inst;
bits<8> num;
let Inst = num;
bits<8> addr;
let Inst = addr;
let isCodeGenOnly = 1;
}
def ALU_CLAUSE : R600WrapperInst <(outs),
(ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
field bits<8> Inst;
bits<8> num;
let Inst = num;
bits<8> addr;
let Inst = addr;
let isCodeGenOnly = 1;
}
@ -1452,8 +1452,8 @@ def CONST_COPY : Instruction {
} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
def TEX_VTX_CONSTBUF :
InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr",
[(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>,
InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "VTX_READ_eg $dst_gpr, $src",
[(set v4i32:$dst_gpr, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$src, (i32 imm:$buffer_id)))]>,
VTX_WORD1_GPR, VTX_WORD0_eg {
let VC_INST = 0;
@ -1506,7 +1506,7 @@ def TEX_VTX_CONSTBUF :
}
def TEX_VTX_TEXBUF:
InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">,
InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst_gpr, $src">,
VTX_WORD1_GPR, VTX_WORD0_eg {
let VC_INST = 0;