forked from OSchip/llvm-project
[AArch64] Add support for various operations on nxv1i1 types.
The supported operations are: * Logical operations (and, or, xor, bic) * Logical reductions (and, or, xor, [us]min, [us]max) * Conversions to/from svbool_t * Predicate count (CNTP) Reviewed By: paulwalker-arm Differential Revision: https://reviews.llvm.org/D128835
This commit is contained in:
Sander de Smalen
parent
e7db82d701
commit
95e08824fa
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@ -1086,8 +1086,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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// SVE and SME.
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if (Subtarget->hasSVE() || Subtarget->hasSME()) {
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for (auto VT :
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{MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::nxv1i1})
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{MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::nxv1i1}) {
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setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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}
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}
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if (Subtarget->hasSVE()) {
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@ -1176,7 +1178,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
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@ -4361,6 +4362,8 @@ SDValue AArch64TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
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static inline SDValue getPTrue(SelectionDAG &DAG, SDLoc DL, EVT VT,
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int Pattern) {
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if (VT == MVT::nxv1i1 && Pattern == AArch64SVEPredPattern::all)
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return DAG.getConstant(1, DL, MVT::nxv1i1);
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return DAG.getNode(AArch64ISD::PTRUE, DL, VT,
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DAG.getTargetConstant(Pattern, DL, MVT::i32));
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}
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@ -21104,6 +21107,11 @@ SDValue AArch64TargetLowering::LowerPredReductionToSVE(SDValue ReduceOp,
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case ISD::VECREDUCE_XOR: {
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SDValue ID =
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DAG.getTargetConstant(Intrinsic::aarch64_sve_cntp, DL, MVT::i64);
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if (OpVT == MVT::nxv1i1) {
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// Emulate a CNTP on .Q using .D and a different governing predicate.
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Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Pg);
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Op = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Op);
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}
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SDValue Cntp =
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DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64, ID, Pg, Op);
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return DAG.getAnyExtOrTrunc(Cntp, DL, VT);
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@ -2139,6 +2139,8 @@ let Predicates = [HasSVEorSME] in {
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(PTEST_PP PPR:$pg, PPR:$src)>;
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def : Pat<(AArch64ptest (nxv2i1 PPR:$pg), (nxv2i1 PPR:$src)),
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(PTEST_PP PPR:$pg, PPR:$src)>;
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def : Pat<(AArch64ptest (nxv1i1 PPR:$pg), (nxv1i1 PPR:$src)),
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(PTEST_PP PPR:$pg, PPR:$src)>;
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let AddedComplexity = 1 in {
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class LD1RPat<ValueType vt, SDPatternOperator operator,
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@ -2404,6 +2406,9 @@ let Predicates = [HasSVEorSME] in {
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(AND_PPzPP (PTRUE_S 31), PPR:$Ps1, PPR:$Ps2)>;
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def : Pat<(nxv2i1 (and PPR:$Ps1, PPR:$Ps2)),
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(AND_PPzPP (PTRUE_D 31), PPR:$Ps1, PPR:$Ps2)>;
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// Emulate .Q operation using a PTRUE_D when the other lanes don't matter.
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def : Pat<(nxv1i1 (and PPR:$Ps1, PPR:$Ps2)),
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(AND_PPzPP (PTRUE_D 31), PPR:$Ps1, PPR:$Ps2)>;
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// Add more complex addressing modes here as required
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multiclass pred_load<ValueType Ty, ValueType PredTy, SDPatternOperator Load,
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@ -1691,6 +1691,9 @@ multiclass sve_int_pred_log<bits<4> opc, string asm, SDPatternOperator op,
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!cast<Instruction>(NAME), PTRUE_S>;
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def : SVE_2_Op_AllActive_Pat<nxv2i1, op_nopred, nxv2i1, nxv2i1,
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!cast<Instruction>(NAME), PTRUE_D>;
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// Emulate .Q operation using a PTRUE_D when the other lanes don't matter.
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def : SVE_2_Op_AllActive_Pat<nxv1i1, op_nopred, nxv1i1, nxv1i1,
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!cast<Instruction>(NAME), PTRUE_D>;
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}
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// An instance of sve_int_pred_log_and but uses op_nopred's first operand as the
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@ -1706,6 +1709,9 @@ multiclass sve_int_pred_log_v2<bits<4> opc, string asm, SDPatternOperator op,
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(!cast<Instruction>(NAME) $Op1, $Op1, $Op2)>;
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def : Pat<(nxv2i1 (op_nopred nxv2i1:$Op1, nxv2i1:$Op2)),
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(!cast<Instruction>(NAME) $Op1, $Op1, $Op2)>;
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// Emulate .Q operation using a PTRUE_D when the other lanes don't matter.
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def : Pat<(nxv1i1 (op_nopred nxv1i1:$Op1, nxv1i1:$Op2)),
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(!cast<Instruction>(NAME) $Op1, $Op1, $Op2)>;
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}
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//===----------------------------------------------------------------------===//
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@ -46,6 +46,15 @@ define <vscale x 16 x i8> @and_b_zero(<vscale x 16 x i8> %a) {
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 1 x i1> @and_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
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; CHECK-LABEL: and_pred_q:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%res = and <vscale x 1 x i1> %a, %b
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ret <vscale x 1 x i1> %res
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}
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define <vscale x 2 x i1> @and_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: and_pred_d:
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; CHECK: // %bb.0:
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@ -126,6 +135,17 @@ define <vscale x 16 x i8> @bic_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 1 x i1> @bic_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
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; CHECK-LABEL: bic_pred_q:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%allones = shufflevector <vscale x 1 x i1> insertelement(<vscale x 1 x i1> undef, i1 true, i32 0), <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
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%not_b = xor <vscale x 1 x i1> %b, %allones
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%res = and <vscale x 1 x i1> %a, %not_b
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ret <vscale x 1 x i1> %res
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}
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define <vscale x 2 x i1> @bic_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: bic_pred_d:
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; CHECK: // %bb.0:
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@ -214,6 +234,15 @@ define <vscale x 16 x i8> @or_b_zero(<vscale x 16 x i8> %a) {
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 1 x i1> @or_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
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; CHECK-LABEL: or_pred_q:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ret
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%res = or <vscale x 1 x i1> %a, %b
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ret <vscale x 1 x i1> %res
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}
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define <vscale x 2 x i1> @or_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: or_pred_d:
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; CHECK: // %bb.0:
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@ -294,6 +323,16 @@ define <vscale x 16 x i8> @xor_b_zero(<vscale x 16 x i8> %a) {
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 1 x i1> @xor_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
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; CHECK-LABEL: xor_pred_q:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.d
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; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%res = xor <vscale x 1 x i1> %a, %b
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ret <vscale x 1 x i1> %res
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}
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define <vscale x 2 x i1> @xor_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
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; CHECK-LABEL: xor_pred_d:
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; CHECK: // %bb.0:
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@ -51,6 +51,19 @@ define i1 @reduce_and_nxv2i1(<vscale x 2 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_and_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_and_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: punpklo p2.h, p1.b
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; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.and.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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; ORV
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define i1 @reduce_or_nxv16i1(<vscale x 16 x i1> %vec) {
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@ -93,6 +106,16 @@ define i1 @reduce_or_nxv2i1(<vscale x 2 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_or_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_or_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.or.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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; XORV
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define i1 @reduce_xor_nxv16i1(<vscale x 16 x i1> %vec) {
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@ -139,6 +162,18 @@ define i1 @reduce_xor_nxv2i1(<vscale x 2 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_xor_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_xor_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: punpklo p1.h, p1.b
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; CHECK-NEXT: cntp x8, p1, p0.d
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.xor.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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; SMAXV
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define i1 @reduce_smax_nxv16i1(<vscale x 16 x i1> %vec) {
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@ -189,6 +224,19 @@ define i1 @reduce_smax_nxv2i1(<vscale x 2 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_smax_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_smax_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: punpklo p2.h, p1.b
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; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.smax.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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; SMINV
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define i1 @reduce_smin_nxv16i1(<vscale x 16 x i1> %vec) {
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@ -231,6 +279,16 @@ define i1 @reduce_smin_nxv2i1(<vscale x 2 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_smin_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_smin_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.smin.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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; UMAXV
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define i1 @reduce_umax_nxv16i1(<vscale x 16 x i1> %vec) {
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@ -273,6 +331,16 @@ define i1 @reduce_umax_nxv2i1(<vscale x 2 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_umax_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_umax_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.umax.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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; UMINV
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define i1 @reduce_umin_nxv16i1(<vscale x 16 x i1> %vec) {
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@ -311,6 +379,19 @@ define i1 @reduce_umin_nxv4i1(<vscale x 4 x i1> %vec) {
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ret i1 %res
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}
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define i1 @reduce_umin_nxv1i1(<vscale x 1 x i1> %vec) {
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; CHECK-LABEL: reduce_umin_nxv1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: punpklo p2.h, p1.b
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; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)
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ret i1 %res
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}
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define i1 @reduce_umin_nxv2i1(<vscale x 2 x i1> %vec) {
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; CHECK-LABEL: reduce_umin_nxv2i1:
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; CHECK: // %bb.0:
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@ -327,33 +408,40 @@ declare i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.and.i1.nxv1i1(<vscale x 1 x i1> %vec)
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declare i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.or.i1.nxv1i1(<vscale x 1 x i1> %vec)
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declare i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.xor.i1.nxv1i1(<vscale x 1 x i1> %vec)
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declare i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.smin.i1.nxv1i1(<vscale x 1 x i1> %vec)
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declare i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.smax.i1.nxv1i1(<vscale x 1 x i1> %vec)
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declare i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)
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declare i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)
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declare i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)
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declare i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)
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declare i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)
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declare i1 @llvm.vector.reduce.umax.i1.nxv1i1(<vscale x 1 x i1> %vec)
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|
|
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@ -44,6 +44,17 @@ define <vscale x 16 x i1> @reinterpret_bool_from_d(<vscale x 2 x i1> %pg) {
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ret <vscale x 16 x i1> %out
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}
|
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|
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define <vscale x 16 x i1> @reinterpret_bool_from_q(<vscale x 1 x i1> %arg) {
|
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; CHECK-LABEL: reinterpret_bool_from_q:
|
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
|
||||
; CHECK-NEXT: punpklo p1.h, p1.b
|
||||
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv1i1(<vscale x 1 x i1> %arg)
|
||||
ret <vscale x 16 x i1> %res
|
||||
}
|
||||
|
||||
;
|
||||
; Converting from svbool_t
|
||||
;
|
||||
|
|
@ -80,6 +91,14 @@ define <vscale x 2 x i1> @reinterpret_bool_to_d(<vscale x 16 x i1> %pg) {
|
|||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 1 x i1> @reinterpret_bool_to_q(<vscale x 16 x i1> %pg) {
|
||||
; CHECK-LABEL: reinterpret_bool_to_q:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %pg)
|
||||
ret <vscale x 1 x i1> %out
|
||||
}
|
||||
|
||||
; Reinterpreting a ptrue should not introduce an `and` instruction.
|
||||
define <vscale x 16 x i1> @reinterpret_ptrue() {
|
||||
; CHECK-LABEL: reinterpret_ptrue:
|
||||
|
|
@ -124,8 +143,10 @@ declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv16i1(<vscale x
|
|||
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)
|
||||
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
|
||||
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)
|
||||
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv1i1(<vscale x 1 x i1>)
|
||||
|
||||
declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv16i1(<vscale x 16 x i1>)
|
||||
declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
|
||||
declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
|
||||
declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
|
||||
declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>)
|
||||
|
|
|
|||
Loading…
Reference in New Issue