maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AMDGPU] Handle mandatory literals in isOperandLegal 

Extend SIInstrInfo::isOperandLegal to enforce a limit on the number of
literal operands for all VALU instructions, not just VOP3. In particular
it now handles VOP2 instructions with a mandatory literal operand like
V_FMAAK_F32.

Differential Revision: https://reviews.llvm.org/D126064
This commit is contained in:
Jay Foad 2022-05-20 13:23:53 +01:00
parent 5b18ef7256
commit 78ec59e6ae
2 changed files with 10 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -4965,9 +4965,9 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
MO = &MI.getOperand(OpIdx);
int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode());
int VOP3LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
int LiteralLimit = !isVOP3(MI) || ST.hasVOP3Literal() ? 1 : 0;
if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--)
if (isLiteralConstantLike(*MO, OpInfo) && !LiteralLimit--)
return false;
SmallDenseSet<RegSubRegPair> SGPRsUsed;
@ -4986,12 +4986,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
return false;
SGPRsUsed.insert(SGPR);
}
} else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
if (--ConstantBusLimit <= 0)
return false;
} else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&
isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
if (!VOP3LiteralLimit--)
} else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 ||
(AMDGPU::isSISrcOperand(InstDesc, i) &&
isLiteralConstantLike(Op, InstDesc.OpInfo[i]))) {
if (!LiteralLimit--)
return false;
if (--ConstantBusLimit <= 0)
return false;

9
llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
View File

@ -1,13 +1,12 @@
; RUN: not --crash llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s 2>&1 | FileCheck %s -check-prefix GFX10
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX10
declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float)
declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg)
; FIXME: This instruction uses two different literal constants which is not
; allowed.
; Check that this constant is not folded into the v_fmaak_f32 instruction.
; GFX10-LABEL: _amdgpu_ps_main:
; GFX10: Bad machine code: VOP2/VOP3 instruction uses more than one literal
; GFX10: instruction: %4:vgpr_32 = nnan nsz arcp contract afn reassoc nofpexcept V_FMAAK_F32 1078530011, %0:vgpr_32, -1077342245, implicit $mode, implicit $exec
; GFX10: v_mov_b32_e32 v1, 0x40490fdb
; GFX10: v_fmaak_f32 v1, v0, v1, 0xbfc90fdb
define amdgpu_ps void @_amdgpu_ps_main(float %arg) {
bb:
%i = fmul reassoc nnan nsz arcp contract afn float %arg, 0x400921FB60000000