maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[GlobalISel] Add big endian support in CallLowering 

When splitting values, CallLowering assumes Lo part goes first. But in big endian ISA such as M68k, Hi part goes first.

This patch fixes this.

Differential Revision: https://reviews.llvm.org/D116877
This commit is contained in:
Sheng 2022-02-08 14:32:48 +00:00 committed by Simon Pilgrim
parent 28669bd091
commit 76c83e747f
2 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
View File

@ -698,10 +698,12 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
ValTy, extendOpFromFlags(Args[i].Flags[0]));
}
bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
for (unsigned Part = 0; Part < NumParts; ++Part) {
Register ArgReg = Args[i].Regs[Part];
// There should be Regs.size() ArgLocs per argument.
VA = ArgLocs[j + Part];
unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
CCValAssign &VA = ArgLocs[j + Idx];
const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
if (VA.isMemLoc() && !Flags.isByVal()) {

6
llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
View File

@ -206,8 +206,8 @@ define i64 @test_ret3(i64 %a) {
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
; CHECK: [[G_UNMERGE_VAL1:%[0-9]+]]:_(s32), [[G_UNMERGE_VAL2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[G_MERGE_VAL]](s64)
; CHECK: $d0 = COPY [[G_UNMERGE_VAL1]](s32)
; CHECK: $d1 = COPY [[G_UNMERGE_VAL2]](s32)
; CHECK: RTS implicit $d0, implicit $d1
; CHECK: $d1 = COPY [[G_UNMERGE_VAL1]](s32)
; CHECK: $d0 = COPY [[G_UNMERGE_VAL2]](s32)
; CHECK: RTS implicit $d1, implicit $d0
ret i64 %a
}