forked from OSchip/llvm-project
[AMDGPU][InstCombine] Remove zero LOD bias
If the bias is zero, we can remove it from the image instruction. Also copy other image optimizations (l->lz, mip->nomip) to IR combines. Differential Revision: https://reviews.llvm.org/D116042
This commit is contained in:
Sebastian Neubauer
parent
0530fdbbbb
commit
603d18033c
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@ -97,10 +97,92 @@ static Value *convertTo16Bit(Value &V, InstCombiner::BuilderTy &Builder) {
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llvm_unreachable("Should never be called!");
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}
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/// Applies Function(II.Args, II.ArgTys) and replaces the intrinsic call with
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/// the modified arguments.
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static Optional<Instruction *> modifyIntrinsicCall(
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IntrinsicInst &II, unsigned NewIntr, InstCombiner &IC,
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std::function<void(SmallVectorImpl<Value *> &, SmallVectorImpl<Type *> &)>
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Func) {
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SmallVector<Type *, 4> ArgTys;
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if (!Intrinsic::getIntrinsicSignature(II.getCalledFunction(), ArgTys))
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return None;
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SmallVector<Value *, 8> Args(II.args());
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// Modify arguments and types
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Func(Args, ArgTys);
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Function *I = Intrinsic::getDeclaration(II.getModule(), NewIntr, ArgTys);
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CallInst *NewCall = IC.Builder.CreateCall(I, Args);
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NewCall->takeName(&II);
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NewCall->copyMetadata(II);
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if (isa<FPMathOperator>(NewCall))
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NewCall->copyFastMathFlags(&II);
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// Erase and replace uses
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if (!II.getType()->isVoidTy())
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IC.replaceInstUsesWith(II, NewCall);
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return IC.eraseInstFromFunction(II);
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}
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static Optional<Instruction *>
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simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
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const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr,
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IntrinsicInst &II, InstCombiner &IC) {
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// Optimize _L to _LZ when _L is zero
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if (const auto *LZMappingInfo =
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AMDGPU::getMIMGLZMappingInfo(ImageDimIntr->BaseOpcode)) {
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if (auto *ConstantLod =
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dyn_cast<ConstantFP>(II.getOperand(ImageDimIntr->LodIndex))) {
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if (ConstantLod->isZero() || ConstantLod->isNegative()) {
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const AMDGPU::ImageDimIntrinsicInfo *NewImageDimIntr =
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AMDGPU::getImageDimIntrinsicByBaseOpcode(LZMappingInfo->LZ,
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ImageDimIntr->Dim);
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return modifyIntrinsicCall(
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II, NewImageDimIntr->Intr, IC, [&](auto &Args, auto &ArgTys) {
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Args.erase(Args.begin() + ImageDimIntr->LodIndex);
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});
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}
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}
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}
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// Optimize _mip away, when 'lod' is zero
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if (const auto *MIPMappingInfo =
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AMDGPU::getMIMGMIPMappingInfo(ImageDimIntr->BaseOpcode)) {
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if (auto *ConstantMip =
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dyn_cast<ConstantInt>(II.getOperand(ImageDimIntr->MipIndex))) {
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if (ConstantMip->isZero()) {
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const AMDGPU::ImageDimIntrinsicInfo *NewImageDimIntr =
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AMDGPU::getImageDimIntrinsicByBaseOpcode(MIPMappingInfo->NONMIP,
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ImageDimIntr->Dim);
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return modifyIntrinsicCall(
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II, NewImageDimIntr->Intr, IC, [&](auto &Args, auto &ArgTys) {
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Args.erase(Args.begin() + ImageDimIntr->MipIndex);
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});
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}
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}
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}
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// Optimize _bias away when 'bias' is zero
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if (const auto *BiasMappingInfo =
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AMDGPU::getMIMGBiasMappingInfo(ImageDimIntr->BaseOpcode)) {
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if (auto *ConstantBias =
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dyn_cast<ConstantFP>(II.getOperand(ImageDimIntr->BiasIndex))) {
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if (ConstantBias->isZero()) {
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const AMDGPU::ImageDimIntrinsicInfo *NewImageDimIntr =
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AMDGPU::getImageDimIntrinsicByBaseOpcode(BiasMappingInfo->NoBias,
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ImageDimIntr->Dim);
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return modifyIntrinsicCall(
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II, NewImageDimIntr->Intr, IC, [&](auto &Args, auto &ArgTys) {
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Args.erase(Args.begin() + ImageDimIntr->BiasIndex);
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ArgTys.erase(ArgTys.begin() + ImageDimIntr->BiasTyArg);
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});
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}
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}
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}
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// Try to use A16 or G16
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if (!ST->hasA16() && !ST->hasG16())
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return None;
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@ -144,43 +226,31 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
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Type *CoordType = FloatCoord ? Type::getHalfTy(II.getContext())
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: Type::getInt16Ty(II.getContext());
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SmallVector<Type *, 4> ArgTys;
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if (!Intrinsic::getIntrinsicSignature(II.getCalledFunction(), ArgTys))
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return None;
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return modifyIntrinsicCall(
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II, II.getIntrinsicID(), IC, [&](auto &Args, auto &ArgTys) {
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ArgTys[ImageDimIntr->GradientTyArg] = CoordType;
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if (!OnlyDerivatives) {
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ArgTys[ImageDimIntr->CoordTyArg] = CoordType;
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ArgTys[ImageDimIntr->GradientTyArg] = CoordType;
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if (!OnlyDerivatives) {
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ArgTys[ImageDimIntr->CoordTyArg] = CoordType;
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// Change the bias type
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if (ImageDimIntr->NumBiasArgs != 0)
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ArgTys[ImageDimIntr->BiasTyArg] = Type::getHalfTy(II.getContext());
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}
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// Change the bias type
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if (ImageDimIntr->NumBiasArgs != 0)
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ArgTys[ImageDimIntr->BiasTyArg] = Type::getHalfTy(II.getContext());
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}
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Function *I =
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Intrinsic::getDeclaration(II.getModule(), II.getIntrinsicID(), ArgTys);
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unsigned EndIndex =
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OnlyDerivatives ? ImageDimIntr->CoordStart : ImageDimIntr->VAddrEnd;
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for (unsigned OperandIndex = ImageDimIntr->GradientStart;
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OperandIndex < EndIndex; OperandIndex++) {
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Args[OperandIndex] =
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convertTo16Bit(*II.getOperand(OperandIndex), IC.Builder);
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}
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SmallVector<Value *, 8> Args(II.args());
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unsigned EndIndex =
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OnlyDerivatives ? ImageDimIntr->CoordStart : ImageDimIntr->VAddrEnd;
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for (unsigned OperandIndex = ImageDimIntr->GradientStart;
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OperandIndex < EndIndex; OperandIndex++) {
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Args[OperandIndex] =
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convertTo16Bit(*II.getOperand(OperandIndex), IC.Builder);
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}
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// Convert the bias
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if (!OnlyDerivatives && ImageDimIntr->NumBiasArgs != 0) {
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Value *Bias = II.getOperand(ImageDimIntr->BiasIndex);
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Args[ImageDimIntr->BiasIndex] = convertTo16Bit(*Bias, IC.Builder);
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}
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CallInst *NewCall = IC.Builder.CreateCall(I, Args);
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NewCall->takeName(&II);
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NewCall->copyMetadata(II);
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if (isa<FPMathOperator>(NewCall))
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NewCall->copyFastMathFlags(&II);
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return IC.replaceInstUsesWith(II, NewCall);
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// Convert the bias
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if (!OnlyDerivatives && ImageDimIntr->NumBiasArgs != 0) {
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Value *Bias = II.getOperand(ImageDimIntr->BiasIndex);
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Args[ImageDimIntr->BiasIndex] = convertTo16Bit(*Bias, IC.Builder);
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}
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});
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}
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bool GCNTTIImpl::canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1,
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@ -131,6 +131,22 @@ def MIMGMIPMappingTable : GenericTable {
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let PrimaryKeyName = "getMIMGMIPMappingInfo";
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}
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class MIMGBiasMapping<MIMGBaseOpcode bias, MIMGBaseOpcode nobias> {
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MIMGBaseOpcode Bias = bias;
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MIMGBaseOpcode NoBias = nobias;
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}
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def MIMGBiasMappingTable : GenericTable {
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let FilterClass = "MIMGBiasMapping";
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let CppTypeName = "MIMGBiasMappingInfo";
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let Fields = ["Bias", "NoBias"];
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string TypeOf_Bias = "MIMGBaseOpcode";
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string TypeOf_NoBias = "MIMGBaseOpcode";
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let PrimaryKey = ["Bias"];
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let PrimaryKeyName = "getMIMGBiasMappingInfo";
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}
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class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> {
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MIMGBaseOpcode G = g;
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MIMGBaseOpcode G16 = g16;
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@ -1140,6 +1156,24 @@ def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>;
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def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>;
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def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>;
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// Bias to NoBias Optimization Mapping
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def : MIMGBiasMapping<IMAGE_SAMPLE_B, IMAGE_SAMPLE>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_B_CL, IMAGE_SAMPLE_CL>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_C_B, IMAGE_SAMPLE_C>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_CL, IMAGE_SAMPLE_C_CL>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_B_O, IMAGE_SAMPLE_O>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_B_CL_O, IMAGE_SAMPLE_CL_O>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_O, IMAGE_SAMPLE_C_O>;
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def : MIMGBiasMapping<IMAGE_SAMPLE_C_B_CL_O, IMAGE_SAMPLE_C_CL_O>;
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def : MIMGBiasMapping<IMAGE_GATHER4_B, IMAGE_GATHER4>;
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def : MIMGBiasMapping<IMAGE_GATHER4_B_CL, IMAGE_GATHER4_CL>;
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def : MIMGBiasMapping<IMAGE_GATHER4_C_B, IMAGE_GATHER4_C>;
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def : MIMGBiasMapping<IMAGE_GATHER4_C_B_CL, IMAGE_GATHER4_C_CL>;
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def : MIMGBiasMapping<IMAGE_GATHER4_B_O, IMAGE_GATHER4_O>;
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def : MIMGBiasMapping<IMAGE_GATHER4_B_CL_O, IMAGE_GATHER4_CL_O>;
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def : MIMGBiasMapping<IMAGE_GATHER4_C_B_O, IMAGE_GATHER4_C_O>;
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def : MIMGBiasMapping<IMAGE_GATHER4_C_B_CL_O, IMAGE_GATHER4_C_CL_O>;
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// G to G16 Optimization Mapping
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def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>;
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@ -132,6 +132,7 @@ bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI) {
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#define GET_MIMGInfoTable_IMPL
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#define GET_MIMGLZMappingTable_IMPL
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#define GET_MIMGMIPMappingTable_IMPL
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#define GET_MIMGBiasMappingTable_IMPL
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#define GET_MIMGG16MappingTable_IMPL
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#include "AMDGPUGenSearchableTables.inc"
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@ -64,6 +64,7 @@ struct GcnBufferFormatInfo {
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#define GET_MIMGEncoding_DECL
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#define GET_MIMGLZMapping_DECL
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#define GET_MIMGMIPMapping_DECL
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#define GET_MIMGBiASMapping_DECL
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#include "AMDGPUGenSearchableTables.inc"
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namespace IsaInfo {
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@ -330,6 +331,11 @@ struct MIMGMIPMappingInfo {
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MIMGBaseOpcode NONMIP;
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};
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struct MIMGBiasMappingInfo {
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MIMGBaseOpcode Bias;
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MIMGBaseOpcode NoBias;
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};
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struct MIMGG16MappingInfo {
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MIMGBaseOpcode G;
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MIMGBaseOpcode G16;
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@ -341,6 +347,9 @@ const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
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LLVM_READONLY
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const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
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LLVM_READONLY
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const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
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LLVM_READONLY
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const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
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@ -66,7 +66,7 @@ define double @test_constant_fold_rcp_f64_43() nounwind {
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define float @test_constant_fold_rcp_f32_43_strictfp() nounwind strictfp {
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; CHECK-LABEL: @test_constant_fold_rcp_f32_43_strictfp(
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; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #[[ATTR12:[0-9]+]]
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; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #[[ATTR14:[0-9]+]]
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; CHECK-NEXT: ret float [[VAL]]
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;
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%val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) strictfp nounwind readnone
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@ -1662,7 +1662,7 @@ define i64 @icmp_constant_inputs_false() {
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define i64 @icmp_constant_inputs_true() {
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; CHECK-LABEL: @icmp_constant_inputs_true(
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; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR13:[0-9]+]]
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; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR15:[0-9]+]]
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; CHECK-NEXT: ret i64 [[RESULT]]
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;
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%result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34)
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@ -2369,7 +2369,7 @@ define i64 @fcmp_constant_inputs_false() {
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define i64 @fcmp_constant_inputs_true() {
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; CHECK-LABEL: @fcmp_constant_inputs_true(
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; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR13]]
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; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR15]]
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; CHECK-NEXT: ret i64 [[RESULT]]
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;
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%result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4)
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@ -2411,7 +2411,7 @@ define i64 @ballot_zero_64() {
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define i64 @ballot_one_64() {
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; CHECK-LABEL: @ballot_one_64(
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; CHECK-NEXT: [[B:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR13]]
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; CHECK-NEXT: [[B:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR15]]
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; CHECK-NEXT: ret i64 [[B]]
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;
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%b = call i64 @llvm.amdgcn.ballot.i64(i1 1)
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@ -2437,7 +2437,7 @@ define i32 @ballot_zero_32() {
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define i32 @ballot_one_32() {
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; CHECK-LABEL: @ballot_one_32(
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; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.read_register.i32(metadata [[META1:![0-9]+]]) #[[ATTR13]]
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; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.read_register.i32(metadata [[META1:![0-9]+]]) #[[ATTR15]]
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; CHECK-NEXT: ret i32 [[B]]
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;
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%b = call i32 @llvm.amdgcn.ballot.i32(i1 1)
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@ -4051,6 +4051,585 @@ define amdgpu_kernel void @image_sample_a16_2darray_nnan(<4 x float> addrspace(1
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ret void
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}
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; --------------------------------------------------------------------
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; llvm.amdgcn.image.sample l to lz
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; --------------------------------------------------------------------
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declare <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2darray.v4f32.f32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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define amdgpu_kernel void @sample_l_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {
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; CHECK-LABEL: @sample_l_1d(
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; CHECK-NEXT: main_body:
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; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32(i32 15, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 15, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %v, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sample_l_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
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; CHECK-LABEL: @sample_l_2d(
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; CHECK-NEXT: main_body:
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; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %s, float %t, float -0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_l_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %lod) {
|
||||
; CHECK-LABEL: @sample_c_l_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32 15, float %zcompare, float %s, float -2.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_l_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @sample_c_l_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_l_o_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %lod) {
|
||||
; CHECK-LABEL: @sample_l_o_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.o.1d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_l_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @sample_l_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_l_o_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %lod) {
|
||||
; CHECK-LABEL: @sample_c_l_o_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_l_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @sample_c_l_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_l_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @gather4_l_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 15, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_c_l_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @gather4_c_l_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_l_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @gather4_l_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_c_l_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
|
||||
; CHECK-LABEL: @gather4_c_l_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_c_l_o_2darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %slice, float %lod) {
|
||||
; CHECK-LABEL: @gather4_c_l_o_2darray(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2darray.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], float [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2darray.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float %slice, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.image.sample mipmap zero
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
define amdgpu_kernel void @load_mip_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i32 %s) {
|
||||
; CHECK-LABEL: @load_mip_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @load_mip_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; CHECK-LABEL: @load_mip_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @load_mip_3d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {
|
||||
; CHECK-LABEL: @load_mip_3d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @load_mip_1darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; CHECK-LABEL: @load_mip_1darray(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @load_mip_2darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {
|
||||
; CHECK-LABEL: @load_mip_2darray(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @load_mip_cube(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {
|
||||
; CHECK-LABEL: @load_mip_cube(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define amdgpu_kernel void @store_mip_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
|
||||
; CHECK-LABEL: @store_mip_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_mip_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
|
||||
; CHECK-LABEL: @store_mip_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_mip_3d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {
|
||||
; CHECK-LABEL: @store_mip_3d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_mip_1darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
|
||||
; CHECK-LABEL: @store_mip_1darray(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: call void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_mip_2darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {
|
||||
; CHECK-LABEL: @store_mip_2darray(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: call void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_mip_cube(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {
|
||||
; CHECK-LABEL: @store_mip_cube(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: call void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #1
|
||||
|
||||
|
||||
declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float>, i32, i32, i32, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.image.sample bias zero
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.b.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f16(i32, i32, half, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
||||
|
||||
define amdgpu_kernel void @sample_b_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
||||
; CHECK-LABEL: @sample_b_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32(i32 15, float 0.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_b_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
|
||||
; CHECK-LABEL: @sample_b_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32(i32 15, float -0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_b_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {
|
||||
; CHECK-LABEL: @sample_c_b_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32(i32 15, float -0.0, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_b_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
|
||||
; CHECK-LABEL: @sample_c_b_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32(i32 15, float 0.0, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_b_o_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s) {
|
||||
; CHECK-LABEL: @sample_b_o_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.o.1d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32(i32 15, i32 %offset, float 0.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_b_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
|
||||
; CHECK-LABEL: @sample_b_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.o.2d.v4f32.f32(i32 15, i32 %offset, float 0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_b_o_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s) {
|
||||
; CHECK-LABEL: @sample_c_b_o_1d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32(i32 15, i32 %offset, float 0.0, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_b_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t) {
|
||||
; CHECK-LABEL: @sample_c_b_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32(i32 15, i32 %offset, float 0.0, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_b_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
|
||||
; CHECK-LABEL: @gather4_b_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32(i32 15, float 0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_c_b_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
|
||||
; CHECK-LABEL: @gather4_c_b_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32(i32 15, float 0.0, float %zcompare,float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_b_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
|
||||
; CHECK-LABEL: @gather4_b_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32(i32 15, i32 %offset, float 0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @gather4_c_b_o_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t) {
|
||||
; CHECK-LABEL: @gather4_c_b_o_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32(i32 15, i32 %offset, float 0.0, float %zcompare,float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sample_c_b_o_a16_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %s, half %t) {
|
||||
; CHECK-LABEL: @sample_c_b_o_a16_2d(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.o.2d.v4f32.f16(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f16(i32 15, i32 %offset, half 0.0, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that bias is not optimized away if > 0
|
||||
define amdgpu_kernel void @sample_b_1d_pos(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
||||
; CHECK-LABEL: @sample_b_1d_pos(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32(i32 15, float 1.000000e+00, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32(i32 15, float 1.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that bias is not optimized away if < 0
|
||||
define amdgpu_kernel void @sample_b_1d_neg(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
||||
; CHECK-LABEL: @sample_b_1d_neg(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32(i32 15, float -1.000000e+00, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32(i32 15, float -1.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; Zero bias + A16
|
||||
define amdgpu_kernel void @sample_b_1d_a16(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
|
||||
; CHECK-LABEL: @sample_b_1d_a16(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
|
||||
; CHECK-NEXT: store <4 x float> [[V]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
main_body:
|
||||
%s32 = fpext half %s to float
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32(i32 15, float -0.0, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
store <4 x float> %v, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.is.shared
|
||||
; --------------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue