forked from OSchip/llvm-project
AMDGPU: Add G_AMDGPU_MAD_64_32 instructions
These generic instructions are trivially selected to V_MAD_[IU]64_[IU]32 instructions when run on the VALU. When at least both factors are scalar, it is usually better to execute some or all of the instruction on the SALU. To this end, we lower the instruction to simpler instructions that are supported on the SALU when applying the register bank mapping. Differential Revision: https://reviews.llvm.org/D124843
This commit is contained in:
Nicolai Hähnle
parent
8e724ad965
commit
5df2893a9a
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@ -458,6 +458,19 @@ bool AMDGPUInstructionSelector::selectG_UADDO_USUBO_UADDE_USUBE(
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return true;
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return true;
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}
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}
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bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32(
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MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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const bool IsUnsigned = I.getOpcode() == AMDGPU::G_AMDGPU_MAD_U64_U32;
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I.setDesc(TII.get(IsUnsigned ? AMDGPU::V_MAD_U64_U32_e64
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: AMDGPU::V_MAD_I64_I32_e64));
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I.addOperand(*MF, MachineOperand::CreateImm(0));
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I.addImplicitDefUseOperands(*MF);
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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// TODO: We should probably legalize these to only using 32-bit results.
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// TODO: We should probably legalize these to only using 32-bit results.
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bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
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bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineBasicBlock *BB = I.getParent();
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@ -3335,6 +3348,9 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
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case TargetOpcode::G_UADDE:
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case TargetOpcode::G_UADDE:
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case TargetOpcode::G_USUBE:
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case TargetOpcode::G_USUBE:
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return selectG_UADDO_USUBO_UADDE_USUBE(I);
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return selectG_UADDO_USUBO_UADDE_USUBE(I);
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case AMDGPU::G_AMDGPU_MAD_U64_U32:
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case AMDGPU::G_AMDGPU_MAD_I64_I32:
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return selectG_AMDGPU_MAD_64_32(I);
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case TargetOpcode::G_INTTOPTR:
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case TargetOpcode::G_INTTOPTR:
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case TargetOpcode::G_BITCAST:
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case TargetOpcode::G_BITCAST:
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case TargetOpcode::G_PTRTOINT:
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case TargetOpcode::G_PTRTOINT:
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@ -97,6 +97,7 @@ private:
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bool selectG_AND_OR_XOR(MachineInstr &I) const;
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bool selectG_AND_OR_XOR(MachineInstr &I) const;
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bool selectG_ADD_SUB(MachineInstr &I) const;
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bool selectG_ADD_SUB(MachineInstr &I) const;
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bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
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bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
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bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
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bool selectG_EXTRACT(MachineInstr &I) const;
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bool selectG_EXTRACT(MachineInstr &I) const;
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bool selectG_MERGE_VALUES(MachineInstr &I) const;
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bool selectG_MERGE_VALUES(MachineInstr &I) const;
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bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
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bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
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@ -1555,6 +1555,157 @@ bool AMDGPURegisterBankInfo::applyMappingBFE(const OperandsMapper &OpdMapper,
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return true;
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return true;
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}
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}
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bool AMDGPURegisterBankInfo::applyMappingMAD_64_32(
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const OperandsMapper &OpdMapper) const {
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MachineInstr &MI = OpdMapper.getMI();
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MachineRegisterInfo &MRI = OpdMapper.getMRI();
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// Insert basic copies.
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applyDefaultMapping(OpdMapper);
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Register Dst0 = MI.getOperand(0).getReg();
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Register Dst1 = MI.getOperand(1).getReg();
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Register Src0 = MI.getOperand(2).getReg();
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Register Src1 = MI.getOperand(3).getReg();
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Register Src2 = MI.getOperand(4).getReg();
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if (MRI.getRegBankOrNull(Src0) == &AMDGPU::VGPRRegBank)
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return true;
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bool IsUnsigned = MI.getOpcode() == AMDGPU::G_AMDGPU_MAD_U64_U32;
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LLT S1 = LLT::scalar(1);
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LLT S32 = LLT::scalar(32);
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bool DstOnValu = MRI.getRegBankOrNull(Src2) == &AMDGPU::VGPRRegBank;
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bool Accumulate = true;
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if (!DstOnValu) {
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if (mi_match(Src2, MRI, m_ZeroInt()))
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Accumulate = false;
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}
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// Keep the multiplication on the SALU.
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MachineIRBuilder B(MI);
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Register DstHi;
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Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0);
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bool MulHiInVgpr = false;
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MRI.setRegBank(DstLo, AMDGPU::SGPRRegBank);
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if (Subtarget.hasSMulHi()) {
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DstHi = IsUnsigned ? B.buildUMulH(S32, Src0, Src1).getReg(0)
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: B.buildSMulH(S32, Src0, Src1).getReg(0);
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MRI.setRegBank(DstHi, AMDGPU::SGPRRegBank);
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} else {
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Register VSrc0 = B.buildCopy(S32, Src0).getReg(0);
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Register VSrc1 = B.buildCopy(S32, Src1).getReg(0);
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MRI.setRegBank(VSrc0, AMDGPU::VGPRRegBank);
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MRI.setRegBank(VSrc1, AMDGPU::VGPRRegBank);
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DstHi = IsUnsigned ? B.buildUMulH(S32, VSrc0, VSrc1).getReg(0)
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: B.buildSMulH(S32, VSrc0, VSrc1).getReg(0);
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MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank);
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if (!DstOnValu) {
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DstHi = buildReadFirstLane(B, MRI, DstHi);
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} else {
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MulHiInVgpr = true;
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}
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}
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// Accumulate and produce the "carry-out" bit.
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//
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// The "carry-out" is defined as bit 64 of the result when computed as a
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// big integer. For unsigned multiply-add, this matches the usual definition
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// of carry-out. For signed multiply-add, bit 64 is the sign bit of the
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// result, which is determined as:
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// sign(Src0 * Src1) + sign(Src2) + carry-out from unsigned 64-bit add
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LLT CarryType = DstOnValu ? S1 : S32;
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const RegisterBank &CarryBank =
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DstOnValu ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank;
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const RegisterBank &DstBank =
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DstOnValu ? AMDGPU::VGPRRegBank : AMDGPU::SGPRRegBank;
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Register Carry;
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Register Zero;
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if (!IsUnsigned) {
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Zero = B.buildConstant(S32, 0).getReg(0);
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MRI.setRegBank(Zero,
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MulHiInVgpr ? AMDGPU::VGPRRegBank : AMDGPU::SGPRRegBank);
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Carry = B.buildICmp(CmpInst::ICMP_SLT, MulHiInVgpr ? S1 : S32, DstHi, Zero)
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.getReg(0);
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MRI.setRegBank(Carry, MulHiInVgpr ? AMDGPU::VCCRegBank
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: AMDGPU::SGPRRegBank);
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if (DstOnValu && !MulHiInVgpr) {
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Carry = B.buildTrunc(S1, Carry).getReg(0);
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MRI.setRegBank(Carry, AMDGPU::VCCRegBank);
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}
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}
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if (Accumulate) {
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if (DstOnValu) {
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DstLo = B.buildCopy(S32, DstLo).getReg(0);
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DstHi = B.buildCopy(S32, DstHi).getReg(0);
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MRI.setRegBank(DstLo, AMDGPU::VGPRRegBank);
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MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank);
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}
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auto Unmerge = B.buildUnmerge(S32, Src2);
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Register Src2Lo = Unmerge.getReg(0);
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Register Src2Hi = Unmerge.getReg(1);
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MRI.setRegBank(Src2Lo, DstBank);
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MRI.setRegBank(Src2Hi, DstBank);
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if (!IsUnsigned) {
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auto Src2Sign = B.buildICmp(CmpInst::ICMP_SLT, CarryType, Src2Hi, Zero);
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MRI.setRegBank(Src2Sign.getReg(0), CarryBank);
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Carry = B.buildXor(CarryType, Carry, Src2Sign).getReg(0);
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MRI.setRegBank(Carry, CarryBank);
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}
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auto AddLo = B.buildUAddo(S32, CarryType, DstLo, Src2Lo);
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DstLo = AddLo.getReg(0);
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Register CarryLo = AddLo.getReg(1);
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MRI.setRegBank(DstLo, DstBank);
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MRI.setRegBank(CarryLo, CarryBank);
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auto AddHi = B.buildUAdde(S32, CarryType, DstHi, Src2Hi, CarryLo);
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DstHi = AddHi.getReg(0);
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MRI.setRegBank(DstHi, DstBank);
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Register CarryHi = AddHi.getReg(1);
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MRI.setRegBank(CarryHi, CarryBank);
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if (IsUnsigned) {
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Carry = CarryHi;
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} else {
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Carry = B.buildXor(CarryType, Carry, CarryHi).getReg(0);
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MRI.setRegBank(Carry, CarryBank);
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}
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} else {
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if (IsUnsigned) {
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Carry = B.buildConstant(CarryType, 0).getReg(0);
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MRI.setRegBank(Carry, CarryBank);
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}
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}
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B.buildMerge(Dst0, {DstLo, DstHi});
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if (DstOnValu) {
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B.buildCopy(Dst1, Carry);
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} else {
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B.buildTrunc(Dst1, Carry);
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}
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MI.eraseFromParent();
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return true;
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}
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// Return a suitable opcode for extending the operands of Opc when widening.
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// Return a suitable opcode for extending the operands of Opc when widening.
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static unsigned getExtendOp(unsigned Opc) {
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static unsigned getExtendOp(unsigned Opc) {
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switch (Opc) {
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switch (Opc) {
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@ -3093,6 +3244,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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case AMDGPU::G_UBFX:
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case AMDGPU::G_UBFX:
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applyMappingBFE(OpdMapper, /*Signed*/ false);
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applyMappingBFE(OpdMapper, /*Signed*/ false);
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return;
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return;
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case AMDGPU::G_AMDGPU_MAD_U64_U32:
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case AMDGPU::G_AMDGPU_MAD_I64_I32:
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applyMappingMAD_64_32(OpdMapper);
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return;
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default:
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default:
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break;
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break;
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}
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}
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@ -3618,6 +3773,48 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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return getDefaultMappingSOP(MI);
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return getDefaultMappingSOP(MI);
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return getDefaultMappingVOP(MI);
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return getDefaultMappingVOP(MI);
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}
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}
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case AMDGPU::G_AMDGPU_MAD_U64_U32:
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case AMDGPU::G_AMDGPU_MAD_I64_I32: {
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// Three possible mappings:
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//
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// - Default SOP
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// - Default VOP
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// - Scalar multiply: src0 and src1 are SGPRs, the rest is VOP.
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//
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// This allows instruction selection to keep the multiplication part of the
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// instruction on the SALU.
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bool AllSalu = true;
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bool MulSalu = true;
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for (unsigned i = 0; i < 5; ++i) {
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Register Reg = MI.getOperand(i).getReg();
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if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {
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if (Bank->getID() != AMDGPU::SGPRRegBankID) {
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AllSalu = false;
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if (i == 2 || i == 3) {
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MulSalu = false;
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break;
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}
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}
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}
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}
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if (AllSalu)
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return getDefaultMappingSOP(MI);
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// If the multiply-add is full-rate in VALU, use that even if the
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// multiplication part is scalar. Accumulating separately on the VALU would
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// take two instructions.
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if (!MulSalu || Subtarget.hasFullRate64Ops())
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return getDefaultMappingVOP(MI);
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// Keep the multiplication on the SALU, then accumulate on the VALU.
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
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OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
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OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
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break;
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}
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case AMDGPU::G_IMPLICIT_DEF: {
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case AMDGPU::G_IMPLICIT_DEF: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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@ -86,6 +86,8 @@ public:
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bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const;
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bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const;
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bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const;
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Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register Reg) const;
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Register Reg) const;
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@ -3110,6 +3110,19 @@ def G_AMDGPU_CLAMP : AMDGPUGenericInstruction {
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let hasSideEffects = 0;
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let hasSideEffects = 0;
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}
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}
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// Integer multiply-add: arg0 * arg1 + arg2.
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//
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// arg0 and arg1 are 32-bit integers (interpreted as signed or unsigned),
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// arg2 is a 64-bit integer. Result is a 64-bit integer and a 1-bit carry-out.
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class G_AMDGPU_MAD_64_32 : AMDGPUGenericInstruction {
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let OutOperandList = (outs type0:$dst, type1:$carry_out);
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let InOperandList = (ins type2:$arg0, type2:$arg1, type0:$arg2);
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let hasSideEffects = 0;
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}
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def G_AMDGPU_MAD_U64_U32 : G_AMDGPU_MAD_64_32;
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def G_AMDGPU_MAD_I64_I32 : G_AMDGPU_MAD_64_32;
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// Atomic cmpxchg. $cmpval ad $newval are packed in a single vector
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// Atomic cmpxchg. $cmpval ad $newval are packed in a single vector
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// operand Expects a MachineMemOperand in addition to explicit
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// operand Expects a MachineMemOperand in addition to explicit
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// operands.
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// operands.
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@ -0,0 +1,48 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
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---
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name: mad_u64_u32_vvv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; GCN-LABEL: name: mad_u64_u32_vvv
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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||||||
|
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3
|
||||||
|
; GCN-NEXT: [[V_MAD_U64_U32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_U64_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_U64_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec
|
||||||
|
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAD_U64_U32_e64_]], implicit [[V_MAD_U64_U32_e64_1]]
|
||||||
|
%0:vgpr(s32) = COPY $vgpr0
|
||||||
|
%1:vgpr(s32) = COPY $vgpr1
|
||||||
|
%2:vgpr(s32) = COPY $vgpr2
|
||||||
|
%3:vgpr(s32) = COPY $vgpr3
|
||||||
|
%4:vgpr(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:vgpr(s64), %6:vcc(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %3
|
||||||
|
S_ENDPGM 0, implicit %5, implicit %6
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_i64_i32_vvv
|
||||||
|
legalized: true
|
||||||
|
regBankSelected: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||||
|
; GCN-LABEL: name: mad_i64_i32_vvv
|
||||||
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||||
|
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||||
|
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3
|
||||||
|
; GCN-NEXT: [[V_MAD_I64_I32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_I64_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec
|
||||||
|
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAD_I64_I32_e64_]], implicit [[V_MAD_I64_I32_e64_1]]
|
||||||
|
%0:vgpr(s32) = COPY $vgpr0
|
||||||
|
%1:vgpr(s32) = COPY $vgpr1
|
||||||
|
%2:vgpr(s32) = COPY $vgpr2
|
||||||
|
%3:vgpr(s32) = COPY $vgpr3
|
||||||
|
%4:vgpr(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:vgpr(s64), %6:vcc(s1) = G_AMDGPU_MAD_I64_I32 %0, %1, %3
|
||||||
|
S_ENDPGM 0, implicit %5, implicit %6
|
||||||
|
...
|
||||||
|
|
@ -0,0 +1,550 @@
|
||||||
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||||
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s
|
||||||
|
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s
|
||||||
|
# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_sss
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; GFX8-LABEL: name: mad_u64_u32_sss
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX8-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; GFX8-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||||
|
; GFX8-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX8-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX8-NEXT: [[UMULH:%[0-9]+]]:vgpr_32(s32) = G_UMULH [[COPY4]], [[COPY5]]
|
||||||
|
; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UMULH]](s32), implicit $exec
|
||||||
|
; GFX8-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX8-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[MUL]], [[UV]]
|
||||||
|
; GFX8-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[V_READFIRSTLANE_B32_]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX8-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||||
|
; GFX9MI-LABEL: name: mad_u64_u32_sss
|
||||||
|
; GFX9MI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX9MI-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; GFX9MI-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||||
|
; GFX9MI-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX9MI-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX9MI-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[MUL]], [[UV]]
|
||||||
|
; GFX9MI-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[UMULH]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX9MI-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX9MI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||||
|
; GFX10-LABEL: name: mad_u64_u32_sss
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||||
|
; GFX10-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX10-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX10-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[MUL]], [[UV]]
|
||||||
|
; GFX10-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[UMULH]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX10-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s32) = COPY $sgpr2
|
||||||
|
%3:_(s32) = COPY $sgpr3
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_ssv
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; GFX8-LABEL: name: mad_u64_u32_ssv
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; GFX8-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; GFX8-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX8-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX8-NEXT: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY4]], [[COPY5]]
|
||||||
|
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[MUL]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UMULH]](s32)
|
||||||
|
; GFX8-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX8-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY6]], [[UV]]
|
||||||
|
; GFX8-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY7]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX8-NEXT: [[MV1:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY8:%[0-9]+]]:vcc(s1) = COPY [[UADDE1]](s1)
|
||||||
|
; GFX9MI-LABEL: name: mad_u64_u32_ssv
|
||||||
|
; GFX9MI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX9MI-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; GFX9MI-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX9MI-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX9MI-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX9MI-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY4]](s32), [[COPY5]], [[MV]]
|
||||||
|
; GFX10-LABEL: name: mad_u64_u32_ssv
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; GFX10-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX10-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[MUL]](s32)
|
||||||
|
; GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UMULH]](s32)
|
||||||
|
; GFX10-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX10-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY4]], [[UV]]
|
||||||
|
; GFX10-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY5]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX10-NEXT: [[MV1:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX10-NEXT: [[COPY6:%[0-9]+]]:vcc(s1) = COPY [[UADDE1]](s1)
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s32) = COPY $vgpr0
|
||||||
|
%3:_(s32) = COPY $vgpr1
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_svs
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_svs
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s64) = COPY [[MV]](s64)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY4]](s32), [[COPY1]], [[COPY5]]
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $vgpr0
|
||||||
|
%2:_(s32) = COPY $sgpr1
|
||||||
|
%3:_(s32) = COPY $sgpr2
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_svv
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_svv
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||||
|
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY4]](s32), [[COPY1]], [[MV]]
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $vgpr0
|
||||||
|
%2:_(s32) = COPY $vgpr1
|
||||||
|
%3:_(s32) = COPY $vgpr2
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_vss
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $sgpr0, $sgpr1, $sgpr2
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_vss
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s64) = COPY [[MV]](s64)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[COPY4]], [[COPY5]]
|
||||||
|
%0:_(s32) = COPY $vgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr0
|
||||||
|
%2:_(s32) = COPY $sgpr1
|
||||||
|
%3:_(s32) = COPY $sgpr2
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_vsv
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $sgpr0, $vgpr1, $vgpr2
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_vsv
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||||
|
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[COPY4]], [[MV]]
|
||||||
|
%0:_(s32) = COPY $vgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s32) = COPY $vgpr1
|
||||||
|
%3:_(s32) = COPY $vgpr2
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_vvs
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_vvs
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s64) = COPY [[MV]](s64)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[COPY1]], [[COPY4]]
|
||||||
|
%0:_(s32) = COPY $vgpr0
|
||||||
|
%1:_(s32) = COPY $vgpr1
|
||||||
|
%2:_(s32) = COPY $sgpr1
|
||||||
|
%3:_(s32) = COPY $sgpr2
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_vvv
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_vvv
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||||
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
|
||||||
|
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[COPY1]], [[MV]]
|
||||||
|
%0:_(s32) = COPY $vgpr0
|
||||||
|
%1:_(s32) = COPY $vgpr1
|
||||||
|
%2:_(s32) = COPY $vgpr2
|
||||||
|
%3:_(s32) = COPY $vgpr3
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_i64_i32_sss
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; GFX8-LABEL: name: mad_i64_i32_sss
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX8-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; GFX8-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||||
|
; GFX8-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX8-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX8-NEXT: [[SMULH:%[0-9]+]]:vgpr_32(s32) = G_SMULH [[COPY4]], [[COPY5]]
|
||||||
|
; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[SMULH]](s32), implicit $exec
|
||||||
|
; GFX8-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX8-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[V_READFIRSTLANE_B32_]](s32), [[C]]
|
||||||
|
; GFX8-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[UV1]](s32), [[C]]
|
||||||
|
; GFX8-NEXT: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[ICMP]], [[ICMP1]]
|
||||||
|
; GFX8-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[MUL]], [[UV]]
|
||||||
|
; GFX8-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[V_READFIRSTLANE_B32_]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX8-NEXT: [[XOR1:%[0-9]+]]:sgpr(s32) = G_XOR [[XOR]], [[UADDE1]]
|
||||||
|
; GFX8-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR1]](s32)
|
||||||
|
; GFX9MI-LABEL: name: mad_i64_i32_sss
|
||||||
|
; GFX9MI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX9MI-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; GFX9MI-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||||
|
; GFX9MI-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX9MI-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX9MI-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SMULH]](s32), [[C]]
|
||||||
|
; GFX9MI-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX9MI-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[UV1]](s32), [[C]]
|
||||||
|
; GFX9MI-NEXT: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[ICMP]], [[ICMP1]]
|
||||||
|
; GFX9MI-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[MUL]], [[UV]]
|
||||||
|
; GFX9MI-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[SMULH]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX9MI-NEXT: [[XOR1:%[0-9]+]]:sgpr(s32) = G_XOR [[XOR]], [[UADDE1]]
|
||||||
|
; GFX9MI-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX9MI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR1]](s32)
|
||||||
|
; GFX10-LABEL: name: mad_i64_i32_sss
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||||
|
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||||
|
; GFX10-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX10-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX10-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SMULH]](s32), [[C]]
|
||||||
|
; GFX10-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[UV1]](s32), [[C]]
|
||||||
|
; GFX10-NEXT: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[ICMP]], [[ICMP1]]
|
||||||
|
; GFX10-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[MUL]], [[UV]]
|
||||||
|
; GFX10-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[SMULH]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX10-NEXT: [[XOR1:%[0-9]+]]:sgpr(s32) = G_XOR [[XOR]], [[UADDE1]]
|
||||||
|
; GFX10-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR1]](s32)
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s32) = COPY $sgpr2
|
||||||
|
%3:_(s32) = COPY $sgpr3
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_I64_I32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_i64_i32_ssv
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; GFX8-LABEL: name: mad_i64_i32_ssv
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; GFX8-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; GFX8-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX8-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX8-NEXT: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY4]], [[COPY5]]
|
||||||
|
; GFX8-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX8-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[SMULH]](s32), [[C]]
|
||||||
|
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[MUL]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[SMULH]](s32)
|
||||||
|
; GFX8-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[UV1]](s32), [[C]]
|
||||||
|
; GFX8-NEXT: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[ICMP1]]
|
||||||
|
; GFX8-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY6]], [[UV]]
|
||||||
|
; GFX8-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY7]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX8-NEXT: [[XOR1:%[0-9]+]]:vcc(s1) = G_XOR [[XOR]], [[UADDE1]]
|
||||||
|
; GFX8-NEXT: [[MV1:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY8:%[0-9]+]]:vcc(s1) = COPY [[XOR1]](s1)
|
||||||
|
; GFX9MI-LABEL: name: mad_i64_i32_ssv
|
||||||
|
; GFX9MI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX9MI-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; GFX9MI-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX9MI-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX9MI-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX9MI-NEXT: [[AMDGPU_MAD_I64_I32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_I64_I32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_I64_I32 [[COPY4]](s32), [[COPY5]], [[MV]]
|
||||||
|
; GFX10-LABEL: name: mad_i64_i32_ssv
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; GFX10-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||||
|
; GFX10-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX10-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SMULH]](s32), [[C]]
|
||||||
|
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[ICMP]](s32)
|
||||||
|
; GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[MUL]](s32)
|
||||||
|
; GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[SMULH]](s32)
|
||||||
|
; GFX10-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)
|
||||||
|
; GFX10-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[UV1]](s32), [[C]]
|
||||||
|
; GFX10-NEXT: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[TRUNC]], [[ICMP1]]
|
||||||
|
; GFX10-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY4]], [[UV]]
|
||||||
|
; GFX10-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY5]], [[UV1]], [[UADDO1]]
|
||||||
|
; GFX10-NEXT: [[XOR1:%[0-9]+]]:vcc(s1) = G_XOR [[XOR]], [[UADDE1]]
|
||||||
|
; GFX10-NEXT: [[MV1:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
|
||||||
|
; GFX10-NEXT: [[COPY6:%[0-9]+]]:vcc(s1) = COPY [[XOR1]](s1)
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s32) = COPY $vgpr0
|
||||||
|
%3:_(s32) = COPY $vgpr1
|
||||||
|
%4:_(s64) = G_MERGE_VALUES %2, %3
|
||||||
|
%5:_(s64), %6:_(s1) = G_AMDGPU_MAD_I64_I32 %0, %1, %4
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_ss0
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $sgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; GFX8-LABEL: name: mad_u64_u32_ss0
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX8-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; GFX8-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX8-NEXT: [[UMULH:%[0-9]+]]:vgpr_32(s32) = G_UMULH [[COPY2]], [[COPY3]]
|
||||||
|
; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UMULH]](s32), implicit $exec
|
||||||
|
; GFX8-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX8-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[MUL]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
||||||
|
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C1]](s32)
|
||||||
|
; GFX9MI-LABEL: name: mad_u64_u32_ss0
|
||||||
|
; GFX9MI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX9MI-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; GFX9MI-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX9MI-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[MUL]](s32), [[UMULH]](s32)
|
||||||
|
; GFX9MI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C1]](s32)
|
||||||
|
; GFX10-LABEL: name: mad_u64_u32_ss0
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX10-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; GFX10-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX10-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[MUL]](s32), [[UMULH]](s32)
|
||||||
|
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C1]](s32)
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s64) = G_CONSTANT i64 0
|
||||||
|
%3:_(s64), %4:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %2
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_u64_u32_vv0
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $vgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_u64_u32_vv0
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[COPY1]], [[COPY2]]
|
||||||
|
%0:_(s32) = COPY $vgpr0
|
||||||
|
%1:_(s32) = COPY $vgpr1
|
||||||
|
%2:_(s64) = G_CONSTANT i64 0
|
||||||
|
%3:_(s64), %4:_(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %2
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_i64_i32_ss0
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $sgpr0, $sgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; GFX8-LABEL: name: mad_i64_i32_ss0
|
||||||
|
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX8-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; GFX8-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||||
|
; GFX8-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||||
|
; GFX8-NEXT: [[SMULH:%[0-9]+]]:vgpr_32(s32) = G_SMULH [[COPY2]], [[COPY3]]
|
||||||
|
; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[SMULH]](s32), implicit $exec
|
||||||
|
; GFX8-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX8-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[V_READFIRSTLANE_B32_]](s32), [[C1]]
|
||||||
|
; GFX8-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[MUL]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
||||||
|
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||||
|
; GFX9MI-LABEL: name: mad_i64_i32_ss0
|
||||||
|
; GFX9MI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX9MI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX9MI-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; GFX9MI-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX9MI-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX9MI-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SMULH]](s32), [[C1]]
|
||||||
|
; GFX9MI-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[MUL]](s32), [[SMULH]](s32)
|
||||||
|
; GFX9MI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||||
|
; GFX10-LABEL: name: mad_i64_i32_ss0
|
||||||
|
; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||||
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||||
|
; GFX10-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; GFX10-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
|
||||||
|
; GFX10-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||||
|
; GFX10-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SMULH]](s32), [[C1]]
|
||||||
|
; GFX10-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[MUL]](s32), [[SMULH]](s32)
|
||||||
|
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||||
|
%0:_(s32) = COPY $sgpr0
|
||||||
|
%1:_(s32) = COPY $sgpr1
|
||||||
|
%2:_(s64) = G_CONSTANT i64 0
|
||||||
|
%3:_(s64), %4:_(s1) = G_AMDGPU_MAD_I64_I32 %0, %1, %2
|
||||||
|
...
|
||||||
|
|
||||||
|
---
|
||||||
|
name: mad_i64_i32_vv0
|
||||||
|
legalized: true
|
||||||
|
|
||||||
|
body: |
|
||||||
|
bb.0:
|
||||||
|
liveins: $vgpr0, $vgpr1
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; CHECK-LABEL: name: mad_i64_i32_vv0
|
||||||
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||||
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||||
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||||
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
|
||||||
|
; CHECK-NEXT: [[AMDGPU_MAD_I64_I32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_I64_I32_1:%[0-9]+]]:vcc(s1) = G_AMDGPU_MAD_I64_I32 [[COPY]](s32), [[COPY1]], [[COPY2]]
|
||||||
|
%0:_(s32) = COPY $vgpr0
|
||||||
|
%1:_(s32) = COPY $vgpr1
|
||||||
|
%2:_(s64) = G_CONSTANT i64 0
|
||||||
|
%3:_(s64), %4:_(s1) = G_AMDGPU_MAD_I64_I32 %0, %1, %2
|
||||||
|
...
|
||||||
Loading…
Reference in New Issue