forked from OSchip/llvm-project
[AMDGPU] Remove the assertion for MUBUF instruction with voffset
Currently, there is an assertion that limits the MUBUF instruction with voffset used for a VGPR spill inside kernel functions when the frame pointer is really used. It seemed more like an unwanted limitation and hence removing the assertion. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D137892
This commit is contained in:
Christudasan Devadasan
parent
1f67dc8b7c
commit
349b6afef4
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@ -1594,7 +1594,6 @@ void SIRegisterInfo::buildSpillLoadStore(
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if (SOffset == AMDGPU::NoRegister) {
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if (!IsFlat) {
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if (UseVGPROffset && ScratchOffsetReg) {
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assert(!FuncInfo->isEntryFunction());
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MIB.addReg(ScratchOffsetReg);
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} else {
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assert(FuncInfo->isEntryFunction());
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@ -0,0 +1,63 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
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# Compiler used to assert when voffset field is enabled in the MUBUF instruction for a VGPR spill inside a kernel body
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# when the frame pointer is enabled. That limitation is now removed and this test should compile without any crash.
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--- |
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define amdgpu_kernel void @kernel_vgpr32_spill() #0 {
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ret void
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}
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attributes #0 = { "frame-pointer"="all"}
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...
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---
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name: kernel_vgpr32_spill
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tracksRegLiveness: true
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stack:
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- { id: 0, type: default, offset: 0, size: 8192, alignment: 8 }
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- { id: 1, type: spill-slot, offset: 0, size: 4, alignment: 4 }
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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frameOffsetReg: $sgpr33
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stackPtrOffsetReg: $sgpr32
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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body: |
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; CHECK-LABEL: name: kernel_vgpr32_spill
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr33 = S_MOV_B32 0
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; CHECK-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
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; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec
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; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0
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S_CMP_EQ_U32 0, 0, implicit-def $scc
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SI_SPILL_V32_SAVE $vgpr0, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, align 4, addrspace 5)
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S_CBRANCH_SCC1 %bb.2, implicit $scc
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bb.1:
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S_NOP 0
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bb.2:
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S_ENDPGM 0
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...
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@ -0,0 +1,94 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -O0 -verify-machineinstrs %s -o - | FileCheck %s
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; The forced spill to preserve the scratch VGPR require the voffset to hold the large offset
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; value in the MUBUF instruction being emitted before s_cbranch_scc1 as it clobbers the SCC.
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define amdgpu_kernel void @test_kernel(i32 %val) #0 {
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; CHECK-LABEL: test_kernel:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s32, 0x180000
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; CHECK-NEXT: s_mov_b32 s33, 0
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: v_writelane_b32 v40, s16, 0
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; CHECK-NEXT: s_mov_b32 s13, s15
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; CHECK-NEXT: s_mov_b32 s12, s14
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; CHECK-NEXT: v_readlane_b32 s14, v40, 0
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; CHECK-NEXT: s_mov_b64 s[16:17], s[8:9]
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; CHECK-NEXT: v_mov_b32_e32 v3, v2
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; CHECK-NEXT: v_mov_b32_e32 v2, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, v0
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; CHECK-NEXT: s_load_dword s8, s[16:17], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_writelane_b32 v40, s8, 1
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def vgpr10
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_add_i32 s34, s33, 0x100100
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; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s34 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b64 s[18:19], 8
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; CHECK-NEXT: s_mov_b32 s8, s16
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; CHECK-NEXT: s_mov_b32 s9, s17
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; CHECK-NEXT: s_mov_b32 s16, s18
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; CHECK-NEXT: s_mov_b32 s15, s19
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; CHECK-NEXT: s_add_u32 s8, s8, s16
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; CHECK-NEXT: s_addc_u32 s15, s9, s15
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; CHECK-NEXT: ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9
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; CHECK-NEXT: s_mov_b32 s9, s15
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; CHECK-NEXT: v_mov_b32_e32 v0, 0x2000
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; CHECK-NEXT: ; implicit-def: $sgpr15
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, device_func@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, device_func@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
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; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
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; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
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; CHECK-NEXT: s_mov_b32 s15, 20
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; CHECK-NEXT: v_lshlrev_b32_e64 v3, s15, v3
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; CHECK-NEXT: s_mov_b32 s15, 10
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; CHECK-NEXT: v_lshlrev_b32_e64 v2, s15, v2
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; CHECK-NEXT: v_or3_b32 v31, v1, v2, v3
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; CHECK-NEXT: ; implicit-def: $sgpr15
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; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
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; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
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; CHECK-NEXT: s_add_i32 s6, s33, 0x100100
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; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s6 ; 4-byte Folded Reload
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; CHECK-NEXT: v_readlane_b32 s4, v40, 1
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; CHECK-NEXT: s_mov_b32 s5, 0
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; CHECK-NEXT: s_cmp_eq_u32 s4, s5
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; CHECK-NEXT: v_mov_b32_e32 v0, 0x4000
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_store_dword v10, v0, s[0:3], s33 offen ; 4-byte Folded Spill
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; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %store
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; CHECK-NEXT: s_add_i32 s5, s33, 0x100000
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; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
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; CHECK-NEXT: ; implicit-def: $sgpr4
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: ds_write_b32 v0, v1
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: .LBB0_2: ; %end
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; CHECK-NEXT: s_endpgm
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%arr = alloca < 1339 x i32>, align 8192, addrspace(5)
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%cmp = icmp ne i32 %val, 0
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%vreg = call i32 asm sideeffect "; def vgpr10", "={v10}"()
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call void @device_func(<1339 x i32> addrspace(5)* %arr)
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br i1 %cmp, label %store, label %end
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store:
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store volatile i32 %vreg, i32 addrspace(3)* undef
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ret void
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end:
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ret void
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}
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declare void @device_func(<1339 x i32> addrspace(5)*)
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attributes #0 = { nounwind "frame-pointer"="all" }
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