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Revert "[VENTUS][RISCV][fix] Fix the float COPY instruction bug" 

This reverts commit 80a3ef9b04.
This commit is contained in:
zhoujingya 2023-10-08 17:35:20 +08:00
parent 0a45eabde0
commit 2b376d146a
4 changed files with 12 additions and 34 deletions
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29
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@ -24,7 +24,6 @@
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/DebugInfoMetadata.h"
@ -146,12 +145,8 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc) const {
const RISCVRegisterInfo *RRI = STI.getRegisterInfo();
// sGPR -> sGPR move
if (RISCV::GPRRegClass.contains(DstReg, SrcReg) &&
RISCVRegisterInfo::hasSGPRs(RRI->getPhysRegClass(DstReg)) &&
RISCVRegisterInfo::hasSGPRs(RRI->getPhysRegClass(SrcReg))) {
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0);
@ -159,9 +154,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
// vGPR -> vGPR move
if (RISCV::VGPRRegClass.contains(DstReg, SrcReg) &&
RISCVRegisterInfo::hasVGPRs(RRI->getPhysRegClass(DstReg)) &&
RISCVRegisterInfo::hasVGPRs(RRI->getPhysRegClass(SrcReg))) {
if (RISCV::VGPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::VADD_VX), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addReg(RISCV::X0);
@ -170,9 +163,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// vGPR -> sGPR move
if (RISCV::GPRRegClass.contains(DstReg) &&
RISCVRegisterInfo::hasSGPRs(RRI->getPhysRegClass(DstReg)) &&
RISCV::VGPRRegClass.contains(SrcReg) &&
RISCVRegisterInfo::hasVGPRs(RRI->getPhysRegClass(SrcReg))) {
RISCV::VGPRRegClass.contains(SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::VMV_X_S), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
@ -180,9 +171,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// vGPR -> sGPRF32 move
if (RISCV::GPRF32RegClass.contains(DstReg) &&
RISCVRegisterInfo::hasFGPRs(RRI->getPhysRegClass(DstReg)) &&
RISCV::VGPRRegClass.contains(SrcReg) &&
RISCVRegisterInfo::hasVGPRs(RRI->getPhysRegClass(SrcReg))) {
RISCV::VGPRRegClass.contains(SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::VFMV_F_S), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
@ -190,9 +179,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// sGPR -> vGPR move
if (RISCV::GPRRegClass.contains(SrcReg) &&
RISCVRegisterInfo::hasSGPRs(RRI->getPhysRegClass(SrcReg)) &&
RISCV::VGPRRegClass.contains(DstReg) &&
RISCVRegisterInfo::hasVGPRs(RRI->getPhysRegClass(DstReg))) {
RISCV::VGPRRegClass.contains(DstReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::VMV_V_X), DstReg)
.addReg(DstReg, RegState::Undef)
.addReg(SrcReg, getKillRegState(KillSrc));
@ -200,10 +187,8 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
// sGPRF32 -> vGPR move
if (RISCV::GPRF32RegClass.contains(SrcReg) &&
RISCVRegisterInfo::hasFGPRs(RRI->getPhysRegClass(SrcReg)) &&
RISCV::VGPRRegClass.contains(DstReg) &&
RISCVRegisterInfo::hasVGPRs(RRI->getPhysRegClass(DstReg))) {
if (RISCV::GPRF32RegClass.contains(SrcReg) &&
RISCV::VGPRRegClass.contains(DstReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::VFMV_S_F), DstReg)
.addReg(DstReg, RegState::Undef)
.addReg(SrcReg, getKillRegState(KillSrc));

1
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
View File

@ -215,7 +215,6 @@ RISCVRegisterInfo::getPhysRegClass(MCRegister Reg) const {
&RISCV::SReg_32RegClass,
*/
&RISCV::VGPRRegClass,
&RISCV::GPRF32RegClass,
&RISCV::GPRRegClass,
};

6
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
View File

@ -21,7 +21,7 @@
namespace llvm {
// This needs to be kept in sync with the field bits in VentusRegisterClass.
enum RISCVRCFlags { IsVGPR = 1 << 0, IsSGPR = 1 << 1, IsFGPR = 1 << 2 }; // enum RISCVRCFlags
enum RISCVRCFlags { IsVGPR = 1 << 0, IsSGPR = 1 << 1 }; // enum RISCVRCFlags
struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
@ -37,10 +37,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
return RC->TSFlags & RISCVRCFlags::IsSGPR;
}
static bool hasFGPRs(const TargetRegisterClass *RC) {
return RC->TSFlags & RISCVRCFlags::IsFGPR;
}
/// Return the 'base' register class for this register.
/// e.g. X5 => SReg_32, V3 => VGPR_32, X5_X6 -> SReg_32, etc.
const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;

10
llvm/lib/Target/RISCV/VentusRegisterInfo.td
View File

@ -32,11 +32,9 @@ class RVRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
// vALU and sALU registers
field bit IsVGPR = 0;
field bit IsSGPR = 0;
field bit IsFGPR = 0;
let TSFlags{0} = IsVGPR;
let TSFlags{1} = IsSGPR;
let TSFlags{2} = IsFGPR;
}
class RISCVReg<bits<8> Enc, string n, list<string> alt = []> : Register<n> {
@ -417,10 +415,10 @@ def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
let RegInfos = XLenRI;
}
let RegInfos = XLenRI, IsFGPR = 1 in {
def GPRF16 : RVRegisterClass<"RISCV", [f16], 16, (add GPR)>;
def GPRF32 : RVRegisterClass<"RISCV", [f32], 32, (add GPR)>;
def GPRF64 : RVRegisterClass<"RISCV", [f64], 64, (add GPR)>;
let RegInfos = XLenRI in {
def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>;
def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
} // RegInfos = XLenRI
let RegAltNameIndices = [ABIRegAltName] in {