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Revert "[AMDGPU] Move SIModeRegisterDefaults to SI MFI" 

Break msan bots. Details in D134666.

This reverts commit 0ce96e06ee.
This commit is contained in:
Vitaly Buka 2022-09-26 22:16:34 -07:00
parent a64bce963d
commit 20a80d60a8
5 changed files with 10 additions and 11 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -1630,12 +1630,12 @@ SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
// float fr = mad(fqneg, fb, fa); // float fr = mad(fqneg, fb, fa);
unsigned OpCode = !Subtarget->hasMadMacF32Insts() ? unsigned OpCode = !Subtarget->hasMadMacF32Insts() ?
(unsigned)ISD::FMA : (unsigned)ISD::FMA :
(!MFI || !MFI->getMode().allFP32Denormals()) ? !MFI->getMode().allFP32Denormals() ?
(unsigned)ISD::FMAD : (unsigned)ISD::FMAD :
(unsigned)AMDGPUISD::FMAD_FTZ; (unsigned)AMDGPUISD::FMAD_FTZ;
SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa); SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);

2
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
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@ -17,7 +17,7 @@
using namespace llvm; using namespace llvm;
AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
: IsEntryFunction(AMDGPU::isEntryFunctionCC( : Mode(MF.getFunction()), IsEntryFunction(AMDGPU::isEntryFunctionCC(
MF.getFunction().getCallingConv())), MF.getFunction().getCallingConv())),
IsModuleEntryFunction( IsModuleEntryFunction(
AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())), AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())),

7
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
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@ -45,6 +45,9 @@ protected:
/// stages. /// stages.
Align DynLDSAlign; Align DynLDSAlign;
// State of MODE register, assumed FP mode.
AMDGPU::SIModeRegisterDefaults Mode;
// Kernels + shaders. i.e. functions called by the hardware and not called // Kernels + shaders. i.e. functions called by the hardware and not called
// by other functions. // by other functions.
bool IsEntryFunction = false; bool IsEntryFunction = false;
@ -77,6 +80,10 @@ public:
return GDSSize; return GDSSize;
} }
AMDGPU::SIModeRegisterDefaults getMode() const {
return Mode;
}
bool isEntryFunction() const { bool isEntryFunction() const {
return IsEntryFunction; return IsEntryFunction;
} }

1
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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@ -31,7 +31,6 @@ using namespace llvm;
SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
: AMDGPUMachineFunction(MF), : AMDGPUMachineFunction(MF),
Mode(MF.getFunction()),
BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())), BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())), ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())), GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),

7
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
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@ -351,9 +351,6 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
class SIMachineFunctionInfo final : public AMDGPUMachineFunction { class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
friend class GCNTargetMachine; friend class GCNTargetMachine;
// State of MODE register, assumed FP mode.
AMDGPU::SIModeRegisterDefaults Mode;
// Registers that may be reserved for spilling purposes. These may be the same // Registers that may be reserved for spilling purposes. These may be the same
// as the input registers. // as the input registers.
Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG; Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
@ -555,10 +552,6 @@ public:
WWMReservedRegs.insert(Reg); WWMReservedRegs.insert(Reg);
} }
AMDGPU::SIModeRegisterDefaults getMode() const {
return Mode;
}
ArrayRef<SIRegisterInfo::SpilledReg> ArrayRef<SIRegisterInfo::SpilledReg>
getSGPRToVGPRSpills(int FrameIndex) const { getSGPRToVGPRSpills(int FrameIndex) const {
auto I = SGPRToVGPRSpills.find(FrameIndex); auto I = SGPRToVGPRSpills.find(FrameIndex);