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[ARM] Add Support for Cortex-M85 

This patch adds support for Arm's Cortex-M85 CPU. The Cortex-M85 CPU is
an Arm v8.1m Mainline CPU, with optional support for MVE and PACBTI,
both of which are enabled by default.

Parts have been coauthored by by Mark Murray, Alexandros Lamprineas and
David Green.

Differential Revision: https://reviews.llvm.org/D128415
This commit is contained in:
Archibald Elliott 2022-07-05 10:43:31 +01:00
parent f6fa998590
commit 1666f09933
11 changed files with 57 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
clang/docs/ReleaseNotes.rst
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@ -537,6 +537,10 @@ DWARF Support in Clang
Arm and AArch64 Support in Clang
--------------------------------
- clang now supports the Cortex-M85 CPU, which can be chosen with
`-mcpu=cortex-m85`. By default, this has PACBTI turned on, but it can be
disabled with `-mcpu=cortex-m85+nopacbti`.
Floating Point Support in Clang
-------------------------------

3
clang/test/CodeGen/arm-target-features.c
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@ -110,4 +110,7 @@
// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m55 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-MAIN-LINUX
// CHECK-ARMV81M-MAIN-LINUX: "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
// CHECK-ARMV81M-CORTEX-M85-LINUX: "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
void foo() {}

3
clang/test/Driver/arm-cortex-cpus-2.c
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@ -559,6 +559,9 @@
// RUN: %clang -target arm -mcpu=cortex-m55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M55 %s
// CHECK-CORTEX-M55: "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} "-target-cpu" "cortex-m55"
// RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M85 %s
// CHECK-CORTEX-M85: "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} "-target-cpu" "cortex-m85"
// RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NEOVERSE-N2 %s
// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" "neoverse-n2"

2
clang/test/Driver/arm-nofp-disabled-features.c
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@ -9,8 +9,10 @@
// RUN: %clang -target arm-arm-none-eabi -mfpu=none %s -### 2>&1 | FileCheck %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8-a+nofp %s -### 2>&1 | FileCheck %s
// RUN: %clang -target arm-arm-none-eabi -mcpu=cortex-a35+nofp %s -### 2>&1 | FileCheck %s
// RUN: %clang -target arm-arm-none-eabi -mcpu=cortex-m85+nofp %s -### 2>&1 | FileCheck %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8-a+nofp+nomve %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-NOMVE
// RUN: %clang -target arm-arm-none-eabi -mcpu=cortex-a35+nofp+nomve %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-NOMVE
// RUN: %clang -target arm-arm-none-eabi -mcpu=cortex-m85+nofp+nomve %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-NOMVE
// CHECK: "-target-feature" "-dotprod"
// CHECK: "-target-feature" "-fp16fml"
// CHECK: "-target-feature" "-bf16"

7
clang/test/Driver/arm-nopacbti-disabled-features.c Normal file
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@ -0,0 +1,7 @@
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+nopacbti %s -### 2>&1 | FileCheck %s
// RUN: %clang -target arm-arm-none-eabi -mcpu=cortex-m85+nopacbti %s -### 2>&1 | FileCheck %s
// CHECK-NOT: "-target-feature" "+pacbti"
// CHECK: "-target-feature" "-pacbti"
// CHECK-NOT: "-target-feature" "+pacbti"

2
clang/test/Misc/target-invalid-cpu-note.c
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@ -1,7 +1,7 @@
// Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if there is anything extra in the output.
// RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix ARM
// ARM: error: unknown target CPU 'not-a-cpu'
// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}}
// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}}
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'

1
llvm/docs/ReleaseNotes.rst
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@ -111,6 +111,7 @@ Changes to the ARM Backend
Erratum 1655431. This is enabled by default when targeting either CPU.
* Implemented generation of Windows SEH unwind information.
* Switched the MinGW target to use SEH instead of DWARF for unwind information.
* Added support for the Cortex-M85 CPU.
Changes to the AVR Backend
--------------------------

3
llvm/include/llvm/Support/ARMTargetParser.def
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@ -303,6 +303,9 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)

7
llvm/lib/Target/ARM/ARM.td
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@ -1450,6 +1450,13 @@ def : ProcessorModel<"cortex-m55", CortexM4Model, [ARMv81mMainline,
HasMVEFloatOps,
FeatureFixCMSE_CVE_2021_35465]>;
def : ProcessorModel<"cortex-m85", CortexM7Model, [ARMv81mMainline,
FeatureDSP,
FeatureFPARMv8_D16,
FeaturePACBTI,
FeatureUseMISched,
HasMVEFloatOps]>;
def : ProcNoItin<"cortex-a32", [ARMv8a,
FeatureHWDivThumb,
FeatureHWDivARM,

19
llvm/test/CodeGen/ARM/build-attributes.ll
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@ -235,6 +235,8 @@
; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=ARMv81M-MAIN-MVEFP
; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+pacbti | FileCheck %s --check-prefix=ARMv81M-MAIN-PACBTI
; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-m55 | FileCheck %s --check-prefix=CORTEX-M55
; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-m85 | FileCheck %s --check-prefix=CORTEX-M85
; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-m85+nopacbti | FileCheck %s --check-prefix=CHECK-NO-PACBTI
; CPU-SUPPORTED-NOT: is not a recognized processor for this target
@ -1748,6 +1750,23 @@
; CORTEX-M55: .eabi_attribute 38, 1
; CORTEX-M55: .eabi_attribute 14, 0
; CORTEX-M85: .cpu cortex-m85
; CORTEX-M85: .eabi_attribute 6, 21 @ Tag_CPU_arch
; CORTEX-M85: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
; CORTEX-M85: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
; CORTEX-M85: .eabi_attribute 9, 3 @ Tag_THUMB_ISA_use
; CORTEX-M85: .fpu fpv5-d16
; CORTEX-M85: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
; CORTEX-M85: .eabi_attribute 48, 2 @ Tag_MVE_arch
; CORTEX-M85: .eabi_attribute 46, 1 @ Tag_DSP_extension
; CORTEX-M85: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
; CORTEX-M85: .eabi_attribute 50, 2 @ Tag_PAC_extension
; CORTEX-M85: .eabi_attribute 52, 2 @ Tag_BTI_extension
; CHECK-NO-PACBTI-NOT: .eabi_attribute 50
; CHECK-NO-PACBTI-NOT: .eabi_attribute 52
define i32 @f(i64 %z) {
ret i32 0
}

8
llvm/unittests/Support/TargetParserTest.cpp
View File

@ -395,13 +395,19 @@ INSTANTIATE_TEST_SUITE_P(
ARM::AEK_FP | ARM::AEK_RAS | ARM::AEK_LOB |
ARM::AEK_FP16,
"8.1-M.Mainline"),
ARMCPUTestParams("cortex-m85", "armv8.1-m.main",
"fp-armv8-fullfp16-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_SIMD |
ARM::AEK_FP | ARM::AEK_RAS | ARM::AEK_LOB |
ARM::AEK_FP16 | ARM::AEK_PACBTI,
"8.1-M.Mainline"),
ARMCPUTestParams("iwmmxt", "iwmmxt", "none", ARM::AEK_NONE, "iwmmxt"),
ARMCPUTestParams("xscale", "xscale", "none", ARM::AEK_NONE, "xscale"),
ARMCPUTestParams("swift", "armv7s", "neon-vfpv4",
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-S")));
static constexpr unsigned NumARMCPUArchs = 88;
static constexpr unsigned NumARMCPUArchs = 89;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;