From 131f7bac63b8cc1700bbae908bdac60f438e69d1 Mon Sep 17 00:00:00 2001 From: Clement Courbet Date: Tue, 7 Sep 2021 09:06:18 +0200 Subject: [PATCH] [llvm-exegesis] Add unit test in preparation for DD109275 --- .../X86/SnippetGeneratorTest.cpp | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp index ce6fd821d2c0..2fd278de07bb 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -154,6 +154,29 @@ TEST_F(X86SerialSnippetGeneratorTest, consumeError(std::move(Error)); } +TEST_F(X86SerialSnippetGeneratorTest, + AvoidSerializingThroughImplicitRegisters) { + // MULX32rr implicitly uses EDX. We should not select that register to avoid + // serialization. + const unsigned Opcode = X86::MULX32rr; + randomGenerator().seed(0); // Initialize seed. + const Instruction &Instr = State.getIC().getInstr(Opcode); + // Forbid all registers but RDX/EDX/DX/DH/DL. The only option would be to + // choose that register, but that would serialize the instruction, so we + // should be returning an error. + auto AllRegisters = State.getRATC().emptyRegisters(); + AllRegisters.flip(); + AllRegisters.reset(X86::RDX); + AllRegisters.reset(X86::EDX); + AllRegisters.reset(X86::DX); + AllRegisters.reset(X86::DH); + AllRegisters.reset(X86::DL); + auto Error = + Generator.generateCodeTemplates(&Instr, AllRegisters).takeError(); + // FIXME: EXPECT_TRUE + consumeError(std::move(Error)). + EXPECT_FALSE((bool)Error); +} + TEST_F(X86SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) { // - CMP64rr // - Op0 Explicit Use RegClass(GR64)