forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix strictfp fmul
This commit is contained in:
Matt Arsenault
parent
fa7477eb87
commit
08ec15e44b
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@ -4827,7 +4827,10 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
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case TargetOpcode::G_FMINNUM_IEEE:
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case TargetOpcode::G_FMAXNUM_IEEE:
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case TargetOpcode::G_FMINIMUM:
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case TargetOpcode::G_FMAXIMUM: {
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case TargetOpcode::G_FMAXIMUM:
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case TargetOpcode::G_STRICT_FADD:
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case TargetOpcode::G_STRICT_FSUB:
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case TargetOpcode::G_STRICT_FMUL: {
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Observer.changingInstr(MI);
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moreElementsVectorSrc(MI, MoreTy, 1);
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moreElementsVectorSrc(MI, MoreTy, 2);
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@ -3712,6 +3712,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case AMDGPU::G_INTRINSIC_TRUNC:
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case AMDGPU::G_STRICT_FADD:
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case AMDGPU::G_STRICT_FSUB:
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case AMDGPU::G_STRICT_FMUL:
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case AMDGPU::G_STRICT_FMA:
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case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar?
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case AMDGPU::G_FSHR: // TODO: Expand for scalar
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@ -145,7 +145,7 @@ let SchedRW = [WriteDoubleAdd] in {
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let FPDPRounding = 1 in {
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defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>;
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defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd>;
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defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul>;
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defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fmul>;
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} // End FPDPRounding = 1
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defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like>;
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defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like>;
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@ -1,8 +1,17 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-GISEL %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX1-GISEL %s
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; FIXME: promotion not handled without f16 insts
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define half @v_constained_fmul_f16_fpexcept_strict(half %x, half %y) #0 {
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@ -63,13 +72,23 @@ define <2 x half> @v_constained_fmul_v2f16_fpexcept_strict(<2 x half> %x, <2 x h
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; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_strict:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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; GFX8-SDAG-LABEL: v_constained_fmul_v2f16_fpexcept_strict:
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; GFX8-SDAG: ; %bb.0:
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; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-SDAG-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
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; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-GISEL-LABEL: v_constained_fmul_v2f16_fpexcept_strict:
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; GFX8-GISEL: ; %bb.0:
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; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-GISEL-NEXT: v_mul_f16_e32 v2, v0, v1
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; GFX8-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 16
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; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
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; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_constained_fmul_v2f16_fpexcept_strict:
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; GFX10PLUS: ; %bb.0:
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@ -88,13 +107,23 @@ define <2 x half> @v_constained_fmul_v2f16_fpexcept_ignore(<2 x half> %x, <2 x h
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; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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; GFX8-SDAG-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
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; GFX8-SDAG: ; %bb.0:
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; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-SDAG-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
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; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-GISEL-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
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; GFX8-GISEL: ; %bb.0:
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; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-GISEL-NEXT: v_mul_f16_e32 v2, v0, v1
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; GFX8-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 16
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; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
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; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
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; GFX10PLUS: ; %bb.0:
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@ -113,13 +142,23 @@ define <2 x half> @v_constained_fmul_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x
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; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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; GFX8-SDAG-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
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; GFX8-SDAG: ; %bb.0:
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; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-SDAG-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
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; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-GISEL-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
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; GFX8-GISEL: ; %bb.0:
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; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-GISEL-NEXT: v_mul_f16_e32 v2, v0, v1
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; GFX8-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 16
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; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
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; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
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; GFX10PLUS: ; %bb.0:
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@ -132,85 +171,165 @@ define <2 x half> @v_constained_fmul_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x
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}
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define <3 x half> @v_constained_fmul_v3f16_fpexcept_strict(<3 x half> %x, <3 x half> %y) #0 {
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; GFX9-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2
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; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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; GFX9-SDAG-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX9-SDAG: ; %bb.0:
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; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v0, v2
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; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mul_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2
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; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
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; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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; GFX9-GISEL-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
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; GFX9-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
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; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10PLUS-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX10PLUS: ; %bb.0:
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; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10PLUS-NEXT: v_pk_mul_f16 v0, v0, v2
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; GFX10PLUS-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
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; GFX8-SDAG-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX8-SDAG: ; %bb.0:
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; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-SDAG-NEXT: v_mul_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
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; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
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; GFX8-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-GISEL-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX8-GISEL: ; %bb.0:
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; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-GISEL-NEXT: v_mul_f16_e32 v4, v0, v2
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; GFX8-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 16
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; GFX8-GISEL-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
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; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; GFX8-GISEL-NEXT: v_bfe_u32 v1, v1, 0, 16
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; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-SDAG-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX10-SDAG: ; %bb.0:
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; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v0, v2
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; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
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; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-GISEL-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX10-GISEL: ; %bb.0:
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; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
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; GFX10-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
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; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-SDAG-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-SDAG-NEXT: v_pk_mul_f16 v0, v0, v2
|
||||
; GFX11-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX1-GISEL-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
|
||||
; GFX1-GISEL: ; %bb.0:
|
||||
; GFX1-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX1-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX1-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
|
||||
; GFX1-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
|
||||
; GFX1-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
%val = call <3 x half> @llvm.experimental.constrained.fmul.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret <3 x half> %val
|
||||
}
|
||||
|
||||
; FIXME: Scalarized
|
||||
define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
|
||||
; GFX9-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX9-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX9-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
|
||||
; GFX9-NEXT: v_perm_b32 v0, v5, v0, s4
|
||||
; GFX9-NEXT: v_perm_b32 v1, v4, v1, s4
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX9-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX9-SDAG: ; %bb.0:
|
||||
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-SDAG-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX9-SDAG-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
|
||||
; GFX9-SDAG-NEXT: v_perm_b32 v0, v5, v0, s4
|
||||
; GFX9-SDAG-NEXT: v_perm_b32 v1, v4, v1, s4
|
||||
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX8-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX8-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
|
||||
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
|
||||
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX9-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX9-GISEL: ; %bb.0:
|
||||
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
|
||||
; GFX9-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
|
||||
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX10-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX10-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX10-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
|
||||
; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX8-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX8-SDAG: ; %bb.0:
|
||||
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-SDAG-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX8-SDAG-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX8-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX8-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v5
|
||||
; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v1, v4
|
||||
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
||||
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
|
||||
; GFX11-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX11-NEXT: v_mul_f16_e32 v2, v6, v5
|
||||
; GFX11-NEXT: v_mul_f16_e32 v3, v7, v4
|
||||
; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
|
||||
; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX8-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX8-GISEL: ; %bb.0:
|
||||
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_e32 v4, v0, v2
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_e32 v2, v1, v3
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, 16
|
||||
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
||||
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
||||
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; GFX8-GISEL-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX10-SDAG: ; %bb.0:
|
||||
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-SDAG-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX10-SDAG-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
|
||||
; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
|
||||
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX10-GISEL: ; %bb.0:
|
||||
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
|
||||
; GFX10-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
|
||||
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
||||
; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
||||
; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
||||
; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
|
||||
; GFX11-SDAG-NEXT: v_mul_f16_e32 v1, v1, v3
|
||||
; GFX11-SDAG-NEXT: v_mul_f16_e32 v0, v0, v2
|
||||
; GFX11-SDAG-NEXT: v_mul_f16_e32 v2, v6, v5
|
||||
; GFX11-SDAG-NEXT: v_mul_f16_e32 v3, v7, v4
|
||||
; GFX11-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
|
||||
; GFX11-SDAG-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
|
||||
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX1-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
|
||||
; GFX1-GISEL: ; %bb.0:
|
||||
; GFX1-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX1-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX1-GISEL-NEXT: v_pk_mul_f16 v0, v0, v2
|
||||
; GFX1-GISEL-NEXT: v_pk_mul_f16 v1, v1, v3
|
||||
; GFX1-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
%val = call <4 x half> @llvm.experimental.constrained.fmul.v4f16(<4 x half> %x, <4 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret <4 x half> %val
|
||||
}
|
||||
|
|
@ -237,17 +356,30 @@ define amdgpu_ps <2 x half> @s_constained_fmul_v2f16_fpexcept_strict(<2 x half>
|
|||
; GFX9-NEXT: v_pk_mul_f16 v0, s2, v0
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX8: ; %bb.0:
|
||||
; GFX8-NEXT: s_lshr_b32 s0, s3, 16
|
||||
; GFX8-NEXT: s_lshr_b32 s1, s2, 16
|
||||
; GFX8-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX8-NEXT: v_mul_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; GFX8-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX8-NEXT: v_mul_f16_e32 v1, s2, v1
|
||||
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
|
||||
; GFX8-NEXT: ; return to shader part epilog
|
||||
; GFX8-SDAG-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX8-SDAG: ; %bb.0:
|
||||
; GFX8-SDAG-NEXT: s_lshr_b32 s0, s3, 16
|
||||
; GFX8-SDAG-NEXT: s_lshr_b32 s1, s2, 16
|
||||
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX8-SDAG-NEXT: v_mul_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX8-SDAG-NEXT: v_mul_f16_e32 v1, s2, v1
|
||||
; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
|
||||
; GFX8-SDAG-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX8-GISEL-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX8-GISEL: ; %bb.0:
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s1, s3, 16
|
||||
; GFX8-GISEL-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s3
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_e32 v1, s0, v1
|
||||
; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 16
|
||||
; GFX8-GISEL-NEXT: v_mul_f16_e32 v0, s2, v0
|
||||
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
||||
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; GFX8-GISEL-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10PLUS-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
|
||||
; GFX10PLUS: ; %bb.0:
|
||||
|
|
@ -264,3 +396,7 @@ declare <4 x half> @llvm.experimental.constrained.fmul.v4f16(<4 x half>, <4 x ha
|
|||
|
||||
attributes #0 = { strictfp }
|
||||
attributes #1 = { inaccessiblememonly nounwind willreturn }
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; GFX10: {{.*}}
|
||||
; GFX11: {{.*}}
|
||||
; GFX8: {{.*}}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
|
||||
|
||||
define float @v_constained_fmul_f32_fpexcept_strict(float %x, float %y) #0 {
|
||||
; GCN-LABEL: v_constained_fmul_f32_fpexcept_strict:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
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define double @v_constained_fmul_f64_fpexcept_strict(double %x, double %y) #0 {
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; GCN-LABEL: v_constained_fmul_f64_fpexcept_strict:
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Loading…
Reference in New Issue