forked from OSchip/llvm-project
[AArch64][SME]: Generate streaming-compatible code for fp-extend-trunc
To generate code compatible to streaming mode: - enable custome lowering for TruncStore to avoid crashing during legalizing TruncStore for non Integer vector. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D138720
This commit is contained in:
Hassnaa Hamdi
parent
5cf6fbc5a0
commit
02db5603ba
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@ -1398,6 +1398,15 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
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if (Subtarget->forceStreamingCompatibleSVE()) {
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setTruncStoreAction(MVT::v2f32, MVT::v2f16, Custom);
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setTruncStoreAction(MVT::v4f32, MVT::v4f16, Custom);
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setTruncStoreAction(MVT::v8f32, MVT::v8f16, Custom);
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setTruncStoreAction(MVT::v1f64, MVT::v1f16, Custom);
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setTruncStoreAction(MVT::v2f64, MVT::v2f16, Custom);
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setTruncStoreAction(MVT::v4f64, MVT::v4f16, Custom);
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setTruncStoreAction(MVT::v1f64, MVT::v1f32, Custom);
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setTruncStoreAction(MVT::v2f64, MVT::v2f32, Custom);
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setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
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for (MVT VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32,
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MVT::v4i32, MVT::v1i64, MVT::v2i64})
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addTypeForStreamingSVE(VT);
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@ -0,0 +1,588 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; FCVT H -> S
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;
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define void @fcvt_v2f16_v2f32(<2 x half>* %a, <2 x float>* %b) #0 {
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; CHECK-LABEL: fcvt_v2f16_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #12]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load <2 x half>, <2 x half>* %a
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%res = fpext <2 x half> %op1 to <2 x float>
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store <2 x float> %res, <2 x float>* %b
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ret void
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}
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define void @fcvt_v4f16_v4f32(<4 x half>* %a, <4 x float>* %b) #0 {
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; CHECK-LABEL: fcvt_v4f16_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldr h0, [x0, #6]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #12]
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; CHECK-NEXT: ldr h0, [x0, #4]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #4]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp]
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; CHECK-NEXT: ldr q0, [sp]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load <4 x half>, <4 x half>* %a
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%res = fpext <4 x half> %op1 to <4 x float>
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store <4 x float> %res, <4 x float>* %b
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ret void
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}
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define void @fcvt_v8f16_v8f32(<8 x half>* %a, <8 x float>* %b) #0 {
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; CHECK-LABEL: fcvt_v8f16_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: ldr h0, [x0, #14]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #28]
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; CHECK-NEXT: ldr h0, [x0, #12]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #24]
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; CHECK-NEXT: ldr h0, [x0, #10]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #20]
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; CHECK-NEXT: ldr h0, [x0, #8]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #16]
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; CHECK-NEXT: ldr h0, [x0, #6]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #12]
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; CHECK-NEXT: ldr h0, [x0, #4]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #4]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp]
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; CHECK-NEXT: ldp q0, q1, [sp]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%op1 = load <8 x half>, <8 x half>* %a
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%res = fpext <8 x half> %op1 to <8 x float>
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store <8 x float> %res, <8 x float>* %b
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ret void
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}
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define void @fcvt_v16f16_v16f32(<16 x half>* %a, <16 x float>* %b) #0 {
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; CHECK-LABEL: fcvt_v16f16_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: ldr h0, [x0, #22]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #60]
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; CHECK-NEXT: ldr h0, [x0, #20]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #56]
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; CHECK-NEXT: ldr h0, [x0, #18]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #52]
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; CHECK-NEXT: ldr h0, [x0, #16]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #48]
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; CHECK-NEXT: ldr h0, [x0, #14]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #44]
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; CHECK-NEXT: ldr h0, [x0, #12]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #40]
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; CHECK-NEXT: ldr h0, [x0, #10]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #36]
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; CHECK-NEXT: ldr h0, [x0, #8]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #32]
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; CHECK-NEXT: ldr h0, [x0, #6]
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; CHECK-NEXT: ldp q1, q3, [sp, #32]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #12]
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; CHECK-NEXT: ldr h0, [x0, #4]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #4]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp]
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; CHECK-NEXT: ldr h0, [x0, #30]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #28]
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; CHECK-NEXT: ldr h0, [x0, #28]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #24]
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; CHECK-NEXT: ldr h0, [x0, #26]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #20]
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; CHECK-NEXT: ldr h0, [x0, #24]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: str s0, [sp, #16]
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; CHECK-NEXT: ldp q0, q2, [sp]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: stp q3, q2, [x1, #32]
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, <16 x half>* %a
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%res = fpext <16 x half> %op1 to <16 x float>
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store <16 x float> %res, <16 x float>* %b
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ret void
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}
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;
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; FCVT H -> D
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;
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define void @fcvt_v1f16_v1f64(<1 x half>* %a, <1 x double>* %b) #0 {
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; CHECK-LABEL: fcvt_v1f16_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%op1 = load <1 x half>, <1 x half>* %a
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%res = fpext <1 x half> %op1 to <1 x double>
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store <1 x double> %res, <1 x double>* %b
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ret void
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}
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define void @fcvt_v2f16_v2f64(<2 x half>* %a, <2 x double>* %b) #0 {
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; CHECK-LABEL: fcvt_v2f16_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp]
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; CHECK-NEXT: ldr q0, [sp]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load <2 x half>, <2 x half>* %a
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%res = fpext <2 x half> %op1 to <2 x double>
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store <2 x double> %res, <2 x double>* %b
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ret void
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}
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define void @fcvt_v4f16_v4f64(<4 x half>* %a, <4 x double>* %b) #0 {
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; CHECK-LABEL: fcvt_v4f16_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: ldr h0, [x0, #6]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #24]
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; CHECK-NEXT: ldr h0, [x0, #4]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #16]
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp]
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; CHECK-NEXT: ldp q0, q1, [sp]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%op1 = load <4 x half>, <4 x half>* %a
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%res = fpext <4 x half> %op1 to <4 x double>
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store <4 x double> %res, <4 x double>* %b
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ret void
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}
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define void @fcvt_v8f16_v8f64(<8 x half>* %a, <8 x double>* %b) #0 {
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; CHECK-LABEL: fcvt_v8f16_v8f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: ldr h0, [x0, #10]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #56]
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; CHECK-NEXT: ldr h0, [x0, #8]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #48]
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; CHECK-NEXT: ldr h0, [x0, #6]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #40]
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; CHECK-NEXT: ldr h0, [x0, #4]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #32]
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: ldp q1, q3, [sp, #32]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp]
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; CHECK-NEXT: ldr h0, [x0, #14]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #24]
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; CHECK-NEXT: ldr h0, [x0, #12]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #16]
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; CHECK-NEXT: ldp q0, q2, [sp]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: stp q3, q2, [x1, #32]
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%op1 = load <8 x half>, <8 x half>* %a
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%res = fpext <8 x half> %op1 to <8 x double>
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store <8 x double> %res, <8 x double>* %b
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ret void
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}
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define void @fcvt_v16f16_v16f64(<16 x half>* %a, <16 x double>* %b) #0 {
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; CHECK-LABEL: fcvt_v16f16_v16f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #128
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; CHECK-NEXT: .cfi_def_cfa_offset 128
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; CHECK-NEXT: ldr h0, [x0, #26]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #24]
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; CHECK-NEXT: ldr h0, [x0, #24]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #16]
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; CHECK-NEXT: ldr h0, [x0, #6]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #88]
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; CHECK-NEXT: ldr h0, [x0, #4]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #80]
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; CHECK-NEXT: ldr h0, [x0, #2]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp]
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; CHECK-NEXT: ldr h0, [x0, #14]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #72]
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; CHECK-NEXT: ldr h0, [x0, #12]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #64]
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; CHECK-NEXT: ldr h0, [x0, #10]
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; CHECK-NEXT: ldp q3, q1, [sp, #64]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #104]
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; CHECK-NEXT: ldr h0, [x0, #8]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #96]
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; CHECK-NEXT: ldr h0, [x0, #22]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #56]
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; CHECK-NEXT: ldr h0, [x0, #20]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #48]
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; CHECK-NEXT: ldr h0, [x0, #18]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #120]
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; CHECK-NEXT: ldr h0, [x0, #16]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #112]
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; CHECK-NEXT: ldr h0, [x0, #30]
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; CHECK-NEXT: ldp q6, q4, [sp, #96]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #40]
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; CHECK-NEXT: ldr h0, [x0, #28]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: str d0, [sp, #32]
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; CHECK-NEXT: ldp q2, q0, [sp]
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; CHECK-NEXT: ldp q7, q5, [sp, #32]
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; CHECK-NEXT: stp q2, q1, [x1]
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; CHECK-NEXT: stp q6, q3, [x1, #32]
|
||||
; CHECK-NEXT: stp q0, q7, [x1, #96]
|
||||
; CHECK-NEXT: stp q4, q5, [x1, #64]
|
||||
; CHECK-NEXT: add sp, sp, #128
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x half>, <16 x half>* %a
|
||||
%res = fpext <16 x half> %op1 to <16 x double>
|
||||
store <16 x double> %res, <16 x double>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FCVT S -> D
|
||||
;
|
||||
|
||||
define void @fcvt_v1f32_v1f64(<1 x float>* %a, <1 x double>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v1f32_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr s0, [x0]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <1 x float>, <1 x float>* %a
|
||||
%res = fpext <1 x float> %op1 to <1 x double>
|
||||
store <1 x double> %res, <1 x double>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v2f32_v2f64(<2 x float>* %a, <2 x double>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v2f32_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sub sp, sp, #16
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||||
; CHECK-NEXT: ldr s0, [x0, #4]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #8]
|
||||
; CHECK-NEXT: ldr s0, [x0]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp]
|
||||
; CHECK-NEXT: ldr q0, [sp]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <2 x float>, <2 x float>* %a
|
||||
%res = fpext <2 x float> %op1 to <2 x double>
|
||||
store <2 x double> %res, <2 x double>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v4f32_v4f64(<4 x float>* %a, <4 x double>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v4f32_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sub sp, sp, #32
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
||||
; CHECK-NEXT: ldr s0, [x0, #12]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #24]
|
||||
; CHECK-NEXT: ldr s0, [x0, #8]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #16]
|
||||
; CHECK-NEXT: ldr s0, [x0, #4]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #8]
|
||||
; CHECK-NEXT: ldr s0, [x0]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp]
|
||||
; CHECK-NEXT: ldp q0, q1, [sp]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: add sp, sp, #32
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x float>, <4 x float>* %a
|
||||
%res = fpext <4 x float> %op1 to <4 x double>
|
||||
store <4 x double> %res, <4 x double>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v8f32_v8f64(<8 x float>* %a, <8 x double>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v8f32_v8f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sub sp, sp, #64
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 64
|
||||
; CHECK-NEXT: ldr s0, [x0, #20]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #56]
|
||||
; CHECK-NEXT: ldr s0, [x0, #16]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #48]
|
||||
; CHECK-NEXT: ldr s0, [x0, #12]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #40]
|
||||
; CHECK-NEXT: ldr s0, [x0, #8]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #32]
|
||||
; CHECK-NEXT: ldr s0, [x0, #4]
|
||||
; CHECK-NEXT: ldp q1, q3, [sp, #32]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #8]
|
||||
; CHECK-NEXT: ldr s0, [x0]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp]
|
||||
; CHECK-NEXT: ldr s0, [x0, #28]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #24]
|
||||
; CHECK-NEXT: ldr s0, [x0, #24]
|
||||
; CHECK-NEXT: fcvt d0, s0
|
||||
; CHECK-NEXT: str d0, [sp, #16]
|
||||
; CHECK-NEXT: ldp q0, q2, [sp]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: stp q3, q2, [x1, #32]
|
||||
; CHECK-NEXT: add sp, sp, #64
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x float>, <8 x float>* %a
|
||||
%res = fpext <8 x float> %op1 to <8 x double>
|
||||
store <8 x double> %res, <8 x double>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FCVT S -> H
|
||||
;
|
||||
|
||||
define void @fcvt_v2f32_v2f16(<2 x float>* %a, <2 x half>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v2f32_v2f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr d0, [x0]
|
||||
; CHECK-NEXT: ptrue p0.s, vl2
|
||||
; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
|
||||
; CHECK-NEXT: st1h { z0.s }, p0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <2 x float>, <2 x float>* %a
|
||||
%res = fptrunc <2 x float> %op1 to <2 x half>
|
||||
store <2 x half> %res, <2 x half>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v4f32_v4f16(<4 x float>* %a, <4 x half>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v4f32_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: ptrue p0.s, vl4
|
||||
; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
|
||||
; CHECK-NEXT: st1h { z0.s }, p0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x float>, <4 x float>* %a
|
||||
%res = fptrunc <4 x float> %op1 to <4 x half>
|
||||
store <4 x half> %res, <4 x half>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v8f32_v8f16(<8 x float>* %a, <8 x half>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v8f32_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: mov x8, #4
|
||||
; CHECK-NEXT: ptrue p0.s, vl4
|
||||
; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
|
||||
; CHECK-NEXT: st1h { z0.s }, p0, [x1]
|
||||
; CHECK-NEXT: fcvt z1.h, p0/m, z1.s
|
||||
; CHECK-NEXT: st1h { z1.s }, p0, [x1, x8, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x float>, <8 x float>* %a
|
||||
%res = fptrunc <8 x float> %op1 to <8 x half>
|
||||
store <8 x half> %res, <8 x half>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FCVT D -> H
|
||||
;
|
||||
|
||||
define void @fcvt_v1f64_v1f16(<1 x double>* %a, <1 x half>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v1f64_v1f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr d0, [x0]
|
||||
; CHECK-NEXT: ptrue p0.d, vl1
|
||||
; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
|
||||
; CHECK-NEXT: st1h { z0.d }, p0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <1 x double>, <1 x double>* %a
|
||||
%res = fptrunc <1 x double> %op1 to <1 x half>
|
||||
store <1 x half> %res, <1 x half>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v2f64_v2f16(<2 x double>* %a, <2 x half>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v2f64_v2f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: ptrue p0.d, vl2
|
||||
; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
|
||||
; CHECK-NEXT: st1h { z0.d }, p0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <2 x double>, <2 x double>* %a
|
||||
%res = fptrunc <2 x double> %op1 to <2 x half>
|
||||
store <2 x half> %res, <2 x half>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v4f64_v4f16(<4 x double>* %a, <4 x half>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v4f64_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: mov x8, #2
|
||||
; CHECK-NEXT: ptrue p0.d, vl2
|
||||
; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
|
||||
; CHECK-NEXT: st1h { z0.d }, p0, [x1]
|
||||
; CHECK-NEXT: fcvt z1.h, p0/m, z1.d
|
||||
; CHECK-NEXT: st1h { z1.d }, p0, [x1, x8, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, <4 x double>* %a
|
||||
%res = fptrunc <4 x double> %op1 to <4 x half>
|
||||
store <4 x half> %res, <4 x half>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FCVT D -> S
|
||||
;
|
||||
|
||||
define void @fcvt_v1f64_v1f32(<1 x double> %op1, <1 x float>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v1f64_v1f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.d, vl1
|
||||
; CHECK-NEXT: fcvt z0.s, p0/m, z0.d
|
||||
; CHECK-NEXT: st1w { z0.d }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%res = fptrunc <1 x double> %op1 to <1 x float>
|
||||
store <1 x float> %res, <1 x float>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v2f64_v2f32(<2 x double> %op1, <2 x float>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v2f64_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.d, vl2
|
||||
; CHECK-NEXT: fcvt z0.s, p0/m, z0.d
|
||||
; CHECK-NEXT: st1w { z0.d }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%res = fptrunc <2 x double> %op1 to <2 x float>
|
||||
store <2 x float> %res, <2 x float>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fcvt_v4f64_v4f32(<4 x double>* %a, <4 x float>* %b) #0 {
|
||||
; CHECK-LABEL: fcvt_v4f64_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: mov x8, #2
|
||||
; CHECK-NEXT: ptrue p0.d, vl2
|
||||
; CHECK-NEXT: fcvt z0.s, p0/m, z0.d
|
||||
; CHECK-NEXT: st1w { z0.d }, p0, [x1]
|
||||
; CHECK-NEXT: fcvt z1.s, p0/m, z1.d
|
||||
; CHECK-NEXT: st1w { z1.d }, p0, [x1, x8, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, <4 x double>* %a
|
||||
%res = fptrunc <4 x double> %op1 to <4 x float>
|
||||
store <4 x float> %res, <4 x float>* %b
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
Loading…
Reference in New Issue