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update .pot files

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GiHub Action Bot 2025-04-02 05:51:09 +00:00
parent 3faab9cfdf
commit 98064d657e
1 changed files with 11 additions and 11 deletions
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source/locale/gettext/SpinalHDL/Sequential logic/memory.pot
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@ -8,7 +8,7 @@ msgid ""
msgstr "" msgstr ""
"Project-Id-Version: SpinalHDL \n" "Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n" "Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-01-06 12:16+0000\n" "POT-Creation-Date: 2025-04-02 05:51+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n" "Language-Team: LANGUAGE <LL@li.org>\n"
@ -370,42 +370,42 @@ msgstr ""
msgid "Shown below are the VHDL definitions of the standard blackboxes used in SpinalHDL:" msgid "Shown below are the VHDL definitions of the standard blackboxes used in SpinalHDL:"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:365 #: ../../SpinalHDL/Sequential logic/memory.rst:366
msgid "As you can see, blackboxes have a technology parameter. To set it, you can use the ``setTechnology`` function on the corresponding memory. There are currently 4 kinds of technologies possible:" msgid "As you can see, blackboxes have a technology parameter. To set it, you can use the ``setTechnology`` function on the corresponding memory. There are currently 4 kinds of technologies possible:"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:368 #: ../../SpinalHDL/Sequential logic/memory.rst:369
msgid "``auto``" msgid "``auto``"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:369 #: ../../SpinalHDL/Sequential logic/memory.rst:370
msgid "``ramBlock``" msgid "``ramBlock``"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:370 #: ../../SpinalHDL/Sequential logic/memory.rst:371
msgid "``distributedLut``" msgid "``distributedLut``"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:371 #: ../../SpinalHDL/Sequential logic/memory.rst:372
msgid "``registerFile``" msgid "``registerFile``"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:373 #: ../../SpinalHDL/Sequential logic/memory.rst:374
msgid "Blackboxing can insert HDL attributes if ``SpinalConfig#setDevice(Device)`` has been configured for your device-vendor." msgid "Blackboxing can insert HDL attributes if ``SpinalConfig#setDevice(Device)`` has been configured for your device-vendor."
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:376 #: ../../SpinalHDL/Sequential logic/memory.rst:377
msgid "The resulting HDL attributes might look like:" msgid "The resulting HDL attributes might look like:"
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:383 #: ../../SpinalHDL/Sequential logic/memory.rst:384
msgid "SpinalHDL tries to support many common memory types provided by well known vendors and devices, however this is an ever moving landscape and project requirements can be very specific in this area." msgid "SpinalHDL tries to support many common memory types provided by well known vendors and devices, however this is an ever moving landscape and project requirements can be very specific in this area."
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:387 #: ../../SpinalHDL/Sequential logic/memory.rst:388
msgid "If this is important to your design flow then check the output HDL for the expected attributes/generic insertion, while consulting your vendor's platform documentation." msgid "If this is important to your design flow then check the output HDL for the expected attributes/generic insertion, while consulting your vendor's platform documentation."
msgstr "" msgstr ""
#: ../../SpinalHDL/Sequential logic/memory.rst:391 #: ../../SpinalHDL/Sequential logic/memory.rst:392
msgid "HDL attributes can also be added manually using the `addAttribute()` :ref:`addAttribute <vhdl-and-verilog-attributes>` mechanism." msgid "HDL attributes can also be added manually using the `addAttribute()` :ref:`addAttribute <vhdl-and-verilog-attributes>` mechanism."
msgstr "" msgstr ""