From eee547d50a7da5290e780b5d2c95d45f76959905 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Mon, 21 Apr 2025 14:01:47 +0200
Subject: [PATCH] [INTERP] More fixes to INSERTQ/EXTRQ opcodes

---
 src/emu/x64run660f.c | 10 ++++++----
 src/emu/x64runf20f.c | 20 +++++++++++---------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c
index 12ba752ae..66524e588 100644
--- a/src/emu/x64run660f.c
+++ b/src/emu/x64run660f.c
@@ -1705,6 +1705,7 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr)
             EmitSignal(emu, SIGILL, (void*)R_RIP, 0);
             #endif
         } else {
+            //TODO: test /0
             GETEX(2);
             tmp8s = F8&0x3f;
             tmp8u = F8&0x3f;
@@ -1720,12 +1721,13 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr)
             EmitSignal(emu, SIGILL, (void*)R_RIP, 0);
             #endif
         } else {
+            //TODO: test/r
             GETGX;
             GETEX(2);
-            tmp8s = GX->ub[0]&0x3f;
-            tmp8u = GX->ub[1]&0x3f;
-            EX->q[0]>>=tmp8u;
-            EX->q[0]&=((1<<(tmp8s+1))-1);
+            tmp8s = EX->ub[0]&0x3f;
+            tmp8u = EX->ub[1]&0x3f;
+            GX->q[0]>>=tmp8u;
+            GX->q[0]&=((1<<(tmp8s+1))-1);
         }
         break;
 
diff --git a/src/emu/x64runf20f.c b/src/emu/x64runf20f.c
index 94a8cb46a..3b09ee54c 100644
--- a/src/emu/x64runf20f.c
+++ b/src/emu/x64runf20f.c
@@ -296,7 +296,7 @@ uintptr_t RunF20F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step)
         }
         break;
 
-    case 0x78:  /* INSERTQ Ex, Gx, ib, ib */
+    case 0x78:  /* INSERTQ Gx, Ex, ib, ib */
         // AMD only
         nextop = F8;
         if(!BOX64ENV(cputype) || !(MODREG)) {
@@ -304,16 +304,17 @@ uintptr_t RunF20F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step)
             EmitSignal(emu, SIGILL, (void*)R_RIP, 0);
             #endif
         } else {
+            //TODO: test /r
             GETGX;
             GETEX(2);
-            tmp8u = F8&0x3f;
             tmp8s = F8&0x3f;
+            tmp8u = F8&0x3f;
             tmp64u = (1<<(tmp8s+1))-1;
-            EX->q[0] &=~(tmp64u<<tmp8u);
-            EX->q[0] |= (GX->q[0]&tmp64u)<<tmp8u;
+            GX->q[0] &=~(tmp64u<<tmp8u);
+            GX->q[0] |= (EX->q[0]&tmp64u)<<tmp8u;
         }
         break;
-    case 0x79:  /* INSERTQ Ex, Gx */
+    case 0x79:  /* INSERTQ Gx, Ex */
         // AMD only
         nextop = F8;
         if(!BOX64ENV(cputype) || !(MODREG)) {
@@ -321,13 +322,14 @@ uintptr_t RunF20F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step)
             EmitSignal(emu, SIGILL, (void*)R_RIP, 0);
             #endif
         } else {
+            //TODO: test /r
             GETGX;
             GETEX(2);
-            tmp8u = GX->ub[8]&0x3f;
-            tmp8s = GX->ub[9]&0x3f;
+            tmp8u = EX->ub[8]&0x3f;
+            tmp8s = EX->ub[9]&0x3f;
             tmp64u = (1<<(tmp8s+1))-1;
-            EX->q[0] &=~(tmp64u<<tmp8u);
-            EX->q[0] |= (GX->q[0]&tmp64u)<<tmp8u;
+            GX->q[0] &=~(tmp64u<<tmp8u);
+            GX->q[0] |= (EX->q[0]&tmp64u)<<tmp8u;
         }
         break;