The DataLayout can calculate alignment of vectors based on the alignment
of the element type and the number of elements. In fact, it is the product
of these two values. The problem is that for vectors of N x i1, this will
return the alignment of N bytes, since the alignment of i1 is 8 bits. The
vector types of vNi1 should be aligned to N bits instead. Provide explicit
alignment for HVX vectors to avoid such complications.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@260680 91177308-0d34-0410-b5e6-96231b3b80d8
This allows ARMv8.2-A to be targeted either by using "armv8.2a" in the
triple, or by using -march=armv8.2-a (or the alias -march=armv8.2a).
The FP16 extension can be enabled with the "+fp16" suffix to the -march
or -mcpu option. This is consistent with the AArch64 option, rather than
the usual ARM option of -mfpu. We have agreed with the team which will
be upstreaming this to GCC that we want to use this new option format
for new architecture extensions for both ARM and AArch64.
Most of the work for this was done by the TargetParser patch in llvm.
Differential Revision: http://reviews.llvm.org/D15040
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@260533 91177308-0d34-0410-b5e6-96231b3b80d8
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_[1248] macros on SystemZ.
This fixes a miscompile of GCC C++11 standard library headers
due to use of those macros in an ABI-changing manner.
See e.g. /usr/include/c++/4.8.5/ext/concurrence.h:
// Compile time constant that indicates prefered locking policy in
// the current configuration.
static const _Lock_policy __default_lock_policy =
#ifdef __GTHREADS
#if (defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) \
&& defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4))
_S_atomic;
#else
_S_mutex;
#endif
#else
_S_single;
#endif
A different choice of __default_lock_policy causes different
sizes of several of the C++11 data structures, which are then
incompatible when inlined in clang-compiled code with what the
(GCC-compiled) external library expects.
This in turn leads to various crashes when using std::thread
in code compiled with clang, as see e.g. via the ThreadPool
unit tests. See PR 26473 for an example.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@259931 91177308-0d34-0410-b5e6-96231b3b80d8
LLVM can now lower TLS access as per the MS ABI on ARM. This enables the
generation of TLS access for Windows on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@259751 91177308-0d34-0410-b5e6-96231b3b80d8
Defined the new AVX512 registers in clang inline asm.
Fixed a bug in the MC subtarget info creation during the parsing of MS asm statement - now it receives the actual CPU and target features information.
Differential Revision: http://reviews.llvm.org/D16757
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@259639 91177308-0d34-0410-b5e6-96231b3b80d8
Patch by H.J. Lu
```
typedef unsigned int gcc_word __attribute__((mode(word)));
```
and
```
typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
```
define the largest unsigned integer types which can be stored in a
general purpose register, which may not be the pointer type. For x32,
they aren't pointer nor unsigned long. We should
1. Make getUnwindWordWidth and getRegisterWidth virtual,
2. Override them for x32, similar to hasInt128Type.
3. Use getRegisterWidth for __attribute__((mode(word)));
This fixes PR 24706.
Reviewers: rnk
Differential Revision: http://reviews.llvm.org/D16779
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Various bits we'd like to use the new ABI actually compile with "-arch armv7k
-miphoneos-version-min=9.0". Not ideal, but also not ridiculous given how
slices work.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@258976 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts commit r258504.
This commit breaks (at least) sparc-rtems -- the OS (RTEMS) used to
override UserLabelPrefix to "", despite the arch (SPARC) having set it
to "_". Now, the OS doesn't override anymore, but the arch sets it to
"_", resulting in the wrong value. I expect this probably breaks other
OSes that overrode to "" before, as well. (Clearly we have some missing
test cases, here...)
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@258894 91177308-0d34-0410-b5e6-96231b3b80d8
This fixes the 'pure virtual function called' failure with ThreadPool in a
clang-built clang. This fixes the llvm-mips-linux builder.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@256240 91177308-0d34-0410-b5e6-96231b3b80d8
It resolves clang selfhosting with std::once() for Cygwin.
FIXME: It may be EmulatedTLS-generic also for X86-Android.
FIXME: Pass EmulatedTLS to LLVM CodeGen from Clang with -femulated-tls.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@256134 91177308-0d34-0410-b5e6-96231b3b80d8
- Removed support for hexagonv3 and earlier.
- Added handling of hexagonv55 and hexagonv60.
- Added handling of target features (hvx, hvx-double).
- Updated paths to reflect current directory layout.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@255502 91177308-0d34-0410-b5e6-96231b3b80d8
Add/Subtract.
The following instructions are added to AArch32 instruction set:
- VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate
Returning High Half
- VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract
Returning High Half
The following instructions are added to AArch64 instruction set:
- SQRDMLAH: Signed Saturating Rounding Doubling Multiply Accumulate
Returning High Half
- SQRDMLSH: Signed Saturating Rounding Doubling Multiply Subtract
Returning High Half
This patch adds intrinsic and ACLE macro support for these instructions,
as well as corresponding tests.
Differential Revision: http://reviews.llvm.org/D14982
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@254250 91177308-0d34-0410-b5e6-96231b3b80d8
Currently, when there is a global register variable in a program that
is bound to an invalid register, clang/llvm prints an error message that
is not very user-friendly.
This commit improves the diagnostic and moves the check that used to be
in the backend to Sema. In addition, it makes changes to error out if
the size of the register doesn't match the declared variable size.
e.g., volatile register int B asm ("rbp");
rdar://problem/23084219
Differential Revision: http://reviews.llvm.org/D13834
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The TargetParser API to get the default FPU and default extensions has
changed so that it can fall back to the architecture in case of a
generic CPU.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@253199 91177308-0d34-0410-b5e6-96231b3b80d8
is not defined for 32bit mode, but __sparcv9 is. Pass down the correct
-target-cpu flags to the backend, so that instruction restrictions are
applied correctly. Pass down the correct -A flag when not using IAS.
The latter is limited to NetBSD targets in this commit.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@252545 91177308-0d34-0410-b5e6-96231b3b80d8
This patch implements two things in front-end for MCU psABI support:
1) "long double type is the same as double."
2) "New predefined C/C++ pre-processor symbols: iamcu and iamcu__.
Differential Revision: http://reviews.llvm.org/D14205
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This sets the mostly expected Darwin default ABI options for these two
platforms. Active changes from these defaults for watchOS are in a later patch.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@251708 91177308-0d34-0410-b5e6-96231b3b80d8
Bradley Smith