The original idea was to implement it all on the driver, but to do that the
driver needs to know the sse level and to do that it has to know the default
features of a cpu.
Benjamin Kramer pointed out that if one day we decide to implement support for
' __attribute__ ((__target__ ("arch=core2")))', then the frontend needs to
keep its knowledge of default features of a cpu.
To avoid duplicating which part of clang handles default cpu features,
it is probably better to handle -mfpmath in the frontend.
For ARM this patch is just a small improvement. Instead of a cpu list, we
check if neon is enabled, which allows us to reject things like
-mcpu=cortex-a9 -mfpu=vfp -mfpmath=neon
For X86, since LLVM doesn't support an independent ssefp feature, we just
make sure the selected -mfpmath matches the sse level.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@188939 91177308-0d34-0410-b5e6-96231b3b80d8
setFeatureEnabled is never called with "32" or "64". The driver never passes it
and mips' getDefaultFeatures sets the Features map directly.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@188913 91177308-0d34-0410-b5e6-96231b3b80d8
This moves the logic for handling -mfoo -mno-foo from the driver to -cc1. It
also changes -cc1 to apply the options in order, fixing pr16943.
The handling of -mno-mmx -msse is now an explicit special case.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@188817 91177308-0d34-0410-b5e6-96231b3b80d8
The previous value was set to match some ancient version of Apple's GCC.
The value should be higher than anything used by Apple's GCC, but we don't
intend for this value to be updated in the future. We have other macros to
identify compiler versions. <rdar://problem/14749599>
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@188700 91177308-0d34-0410-b5e6-96231b3b80d8
This patch adds -mmsa and -mno-msa to the options supported by
clang to enable and disable support for MSA.
When MSA is enabled, a predefined macro '__mips_msa' is defined to 1.
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@188184 91177308-0d34-0410-b5e6-96231b3b80d8
Patch by Ana Pazos
- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise
- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic
- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same
- Intial implementation of instruction class:
Scalar Arithmetic
- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.
- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@187568 91177308-0d34-0410-b5e6-96231b3b80d8
This patch provides basic support for powerpc64le as an LLVM target.
However, use of this target will not actually generate little-endian
code. Instead, use of the target will cause the correct little-endian
built-in defines to be generated, so that code that tests for
__LITTLE_ENDIAN__, for example, will be correctly parsed for
syntax-only testing. Code generation will otherwise be the same as
powerpc64 (big-endian), for now.
The patch leaves open the possibility of creating a little-endian
PowerPC64 back end, but there is no immediate intent to create such a
thing.
The new test case variant ensures that correct built-in defines for
little-endian code are generated.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@187180 91177308-0d34-0410-b5e6-96231b3b80d8
this code. These aren't technically standard predefines for the platform
but apparantly lots of folks use them as they show up within LLVM's own
codebase. ;] This may even fix some self host issues w/ the JIT!!!
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@184830 91177308-0d34-0410-b5e6-96231b3b80d8
Some embedded targets use ARM's AAPCS with iOS header files that define size_t
as unsigned long, which conflicts with the usual AAPCS definition of size_t
as unsigned int.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@184171 91177308-0d34-0410-b5e6-96231b3b80d8
Just like on Linux, FreeBSD/armv6 assumes the system supports
ldrex/strex unconditionally. It is also used by the kernel. We can
therefore enable support for it, like we do on Linux.
While there, change one of the unit tests to explicitly test against
armv5 instead of armv7, as it actually tests whether libcalls are
emitted.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@184040 91177308-0d34-0410-b5e6-96231b3b80d8
We're getting reports of this warning getting triggered in cases where it
is not adding any value. There is no asm operand modifier that you can use
to silence it, and there's really nothing wrong with having an LDRB, for
example, with a "char" output.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@183172 91177308-0d34-0410-b5e6-96231b3b80d8
This matches gcc's behaviour. The patch also explicitly parses the version so
that this keeps working when we add support for v8.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@181750 91177308-0d34-0410-b5e6-96231b3b80d8
This is safe given how the pre-v6 atomic ops funcions in libgcc are
implemented.
This fixes pr15429.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@181728 91177308-0d34-0410-b5e6-96231b3b80d8
This patch then adds all the usual platform-specific pieces for SystemZ:
driver support, basic target info, register names and constraints,
ABI info and vararg support. It also adds new tests to verify pre-defined
macros and inline asm, and updates a test for the minimum alignment change.
This version of the patch incorporates feedback from reviews by
Eric Christopher and John McCall. Thanks to all reviewers!
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@181211 91177308-0d34-0410-b5e6-96231b3b80d8
The SPARC v8 and SPARC v8 architectures are very similar, so use a base
class to share most information between them.
Include operating systems with known SPARC v9 ports.
Also fix two issues with the SPARC v8 data layout string: SPARC v8 is a
big endian target with a 64-bit aligned stack.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@179596 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the custom lowering code dealing with it, disallow it in PNaclTargetInfo
and adjust tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@179059 91177308-0d34-0410-b5e6-96231b3b80d8
The prefixes and names used are now identical to 32-bit ARM, which is also
expected to remain unchanged.
If we made this change after a release, we'd probably have to support both
variants for a while, but I think since AArch64 exists only on trunk now, it's
acceptable to simply swap them now.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@178870 91177308-0d34-0410-b5e6-96231b3b80d8
Rafael Espindola